Fifo Receive Bound Register (Frbr); Tfwr Field Descriptions; Frbr Field Descriptions - Motorola ColdFire MCF5281 User Manual

Bits
31–2
1–0

17.5.4.19 FIFO Receive Bound Register (FRBR)

The FRBR is an 8-bit register that the user can read to determine the upper address bound
of the FIFO RAM. Drivers can use this value, along with the FRSR to appropriately divide
the available FIFO RAM between the transmit and receive data paths.
31
Field
Reset
R/W
15
Field
Reset
R/W
Address
Figure 17-22. FIFO Receive Bound Register (FRBR)
Bits
31–10
9–2
1–0
MOTOROLA
Table 17-30. TFWR Field Descriptions
Name
— Reserved, should be cleared.
X_WMRK Number of bytes written to transmit FIFO before transmission
of a frame begins
0x 64 bytes written
10 128 bytes written
11 192 bytes written
0000_0000_0000_0000
10 9
—
0000_0110_0000_0000
IPSBAR + 0x114C
Table 17-31. FRBR Field Descriptions
Name
— Reserved, read as 0 (except bit 10, which is read as 1).
R_BOUND Read-only. Highest valid FIFO RAM address.
— Reserved, should be cleared.
Chapter 17. Fast Ethernet Controller (FEC)
Descriptions
—
Read Only
R_BOUND
Read Only
Descriptions
Programming Model
16
2 1 0
—
17-41