Burst Write Sdram Access - Motorola ColdFire MCF5281 User Manual

CLKOUT
A[31:0]
SRAS
SCAS
t
CASL
DRAMW
D[31:0]
SDRAM_CS[0] or [1]
BS[3:0]
Accesses in synchronous burst page mode always cause the following sequence:
1. command
ACTV
2. commands to assure SRAS-to-SCAS delay (if CAS latency is 1, there are no
NOP
commands).
NOP
3. Required number of
given port size.
4. Some transfers need more
5. command
PALL
6. Required number of idle clocks inserted to assure precharge-to-
15.2.3.5 Auto-Refresh Operation
The DRAM controller is equipped with a refresh counter and control. This logic is
responsible for providing timing and control to refresh the SDRAM without user
interaction. Once the refresh counter is set, and refresh is enabled, the counter counts to
zero. At this time, an internal refresh request flag is set and the counter begins counting
down again. The DRAM controller completes any active burst operation and then performs
a operation. The DRAM controller then initiates a refresh cycle and clears the refresh
PALL
MOTOROLA
Row Column Column Column
= 2
ACTV NOP WRITE
Figure 15-7. Burst Write SDRAM Access
or
READ WRITE
commands to assure the
NOP
Chapter 15. Synchronous DRAM Controller Module
t
RWL
WRITE WRITE WRITE
commands to service the transfer size with the
SDRAM Controller Operation
Column
t
RP
NOP PALL
-to-precharge delay.
ACTV
delay.
ACTV
15-15