Jtag And Boundary Scan Timing; Test Clock Input Timing - Motorola ColdFire MCF5281 User Manual

33.15 JTAG and Boundary Scan Timing

Table 33-23. JTAG and Boundary Scan Timing
Num
1 TCLK Frequency of Operation
2 TCLK Cycle Period
3 TCLK Clock Pulse Width
4 TCLK Rise and Fall Times
5 Boundary Scan Input Data Setup Time to TCLK Rise
6 Boundary Scan Input Data Hold Time after TCLK Rise
7 TCLK Low to Boundary Scan Output Data Valid
8 TCLK Low to Boundary Scan Output High Z
9 TMS, TDI Input Data Setup Time to TCLK Rise
10 TMS, TDI Input Data Hold Time after TCLK Rise
11 TCLK Low to TDO Data Valid
12 TCLK Low to TDO High Z
13 TRST Assert Time
14 TRST Setup Time (Negation) to TCLK High
1
JTAG_EN is expected to be a static signal. Hence, it is not associated with any timing
TCLK
(input)
MOTOROLA
1
Characteristics
3
V
IH
V
IL
4
Figure 33-15. Test Clock Input Timing
Chapter 33. Electrical Characteristics
JTAG and Boundary Scan Timing
Symbol
f
JCYC
t
JCYC
t
JCW
t
JCRF
t
BSDST
t
BSDHT
t
BSDV
t
BSDZ
t
TAPBST
t
TAPBHT
t
TDODV
t
TDODZ
t 100.0
TRSTAT
t
TRSTST
2
3
4
Min Max Unit
DC 1/4 f
sys
4 — t
CYC
25.0 — ns
0.0 3.0 ns
5.0 — ns
25.0 — ns
0.0 30.0 ns
0.0 30.0 ns
5.0 — ns
10.0 — ns
0.0 25.0 ns
0.0 8.0 ns
— ns
10.0 — ns
33-25