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Read GPTCn Registers
Write GPTCn Registers
20.5.7 GPT Toggle-On-Overflow Register (GPTTOV)
Field
Reset
R/W
Address
Figure 20-9. GPT Toggle-On-Overflow Register (GPTTOV)
Bit(s)
Name
7–4
—
3–0
TOV
20.5.8 GPT Control Register 1 (GPTCTL1)
Field
OM3
Reset
R/W
Address
Figure 20-10. GPT Control Register 1 (GPTCTL1)
MOTOROLA
Chapter 20. General Purpose Timer Modules (GPTA and GPTB)
Write GPTFLG1 Register
CnF
TFFCA
Figure 20-8. Fast Clear Flag Logic
7
6
5
—
IPSBAR + 0x1A_0008, 0x1B_0008
Table 20-10. GPTTOV Field Description
Reserved, should be cleared.
Toggles the output compare pin on overflow for each channel. This feature only takes
effect when in output compare mode. When set, it takes precedence over forced output
compare but not channel 3 override events. These bits are read anytime, write
anytime.
1 Toggle output compare pin on overflow feature enabled
0 Toggle output compare pin on overflow feature disabled
7
6
5
OL3
OM2
IPSBAR + 0x1A_0009, 0x1B_0009
Data Bit n
4
3
0000_0000
R/W
Description
4
3
2
OL2
OM1
OL1
0000_0000
R/W
Memory Map and Registers
Clear
CnF Flag
0
TOV
1
0
OM0
OL0
20-9
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