Address Error Exception; Illegal Instruction Exception; Divide-By-Zero; Privilege Violation - Motorola ColdFire MCF5281 User Manual

Processor Exceptions
The V2 ColdFire processor uses an imprecise reporting mechanism for access errors on
operand writes. Because the actual write cycle may be decoupled from the processor's
issuing of the operation, the signaling of an access error appears to be decoupled from the
instruction that generated the write. Accordingly, the PC contained in the exception stack
frame merely represents the location in the program when the access error was signaled. All
programming model updates associated with the write instruction are completed. The NOP
instruction can collect access errors for writes. This instruction delays its execution until all
previous operations, including all pending write operations, are complete. If any previous
write terminates with an access error, it is guaranteed to be reported on the NOP instruction.
2.7.2

Address Error Exception

Any attempted execution transferring control to an odd instruction address (that is, if bit 0
of the target address is set) results in an address error exception.
Any attempted use of a word-sized index register (Xn.w) or a scale factor of 8 on an indexed
effective addressing mode generates an address error as does an attempted execution of a
full-format indexed addressing mode.
2.7.3

Illegal Instruction Exception

Any attempted execution of an illegal 16-bit opcode (except for line-A and line-F opcodes)
generates an illegal instruction exception (vector 4). Additionally, any attempted execution
of any non-MAC line-A and most line-F opcode generates their unique exception types,
vector numbers 10 and 11, respectively. The V2 core does not provide illegal instruction
detection on the extension words on any instruction, including MOVEC.
2.7.4

Divide-By-Zero

Attempting to divide by zero causes an exception (vector 5, offset = 0x014).
2.7.5

Privilege Violation

The attempted execution of a supervisor mode instruction while in user mode generates a
privilege violation exception. See the ColdFire Programmer's Reference Manual for lists
of supervisor- and user-mode instructions.
2.7.6

Trace Exception

To aid in program
instruction-by-instruction tracing capability. While in trace mode, indicated by the
assertion of the T-bit in the status register (SR[15] = 1), the completion of an instruction
execution (for all but the STOP instruction) signals a trace exception. This functionality
allows a debugger to monitor program execution.
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development, all
MCF5282 User's Manual
ColdFire processors provide an
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