Use caution when mixing digital and analog inputs. They
should be isolated as much as possible. Rise and fall times
should be as large as possible to minimize ac coupling effects.
7
Field
Reset
R/W:
Address
Figure 27-6. QADC Port QA Data Direction Register (DDRQA)
7
Field
Reset
R/W
Address
Figure 27-7. Port QB Data Direction Register (DDRQB)
27.6.5 Control Registers
This subsection describes the QADC control registers.
27.6.5.1 QADC Control Register 0 (QACR0)
QACR0 establishes the QADC sampling clock (QCLK) with prescaler parameter fields and
defines whether external multiplexing is enabled. Typically, these bits are written once
when the QADC is initialized and not changed thereafter. The bits in this register are read
anytime, write anytime (except during stop mode).
MOTOROLA
6
5
—
DDQA4
R
IPSBAR + 0x19_0008
6
5
—
IPSBAR + 0x19_0009
Chapter 27. Queued Analog-to-Digital Converter (QADC)
NOTE
4
3
DDQA3
0000_0000
R/W
4
3
DDQB3
DDQB2
0000_0000
R
Register Descriptions
2
1
0
—
DDQA1
DDQA0
R
R/W
2
1
0
DDQB1
DDQB0
27-11