Mcf5282 To Sdram Interface (32-Bit Port, 12-Column Address Lines); Connections For External Memory Port Sizes; Sdram Hardware Connections - Motorola ColdFire MCF5281 User Manual

Table 15-23. MCF5282 to SDRAM Interface (32-Bit Port, 12-Column Address Lines)
MCF5282
Pins
Row
Column
SDRAM
Pins
15.2.3.2 SDRAM Byte Strobe Connections
Figure 15-5 shows SDRAM connections for port sizes of 32, 16, or 8 bits.
Figure 15-5. Connections for External Memory Port Sizes
15.2.3.3 Interfacing Example
The tables in the previous section can be used to configure the interface in the following
example. To interface one 2M x 32-bit x 4 bank SDRAM component (8 columns) to the
MCF5282, the connections shown in Table 15-24 would be used.
SDRAM A0 A1
Pins
MCF5282 A15 A14
Pins
15.2.3.4 Burst Page Mode
SDRAM can efficiently provide data when an SDRAM page is opened. As soon as SCAS
is issued, the SDRAM accepts a new address and asserts SCAS every CLKOUT for as long
as accesses occur in that page. In burst page mode, there are multiple read or write
operations for every
MOTOROLA
A15 A14 A13 A12
15 14 13 12
2 3 4 5
A0 A1 A2 A3
Byte Enable BS3
Processor
D[31:24]
External
Data Bus
32-Bit Port
Byte 0
Memory
16-Bit Port
Byte 0
Memory
Byte 2
8-Bit Port
Byte 0
Memory
Byte 1
Byte 2
Byte 3
Table 15-24. SDRAM Hardware Connections
A2 A3 A4 A5
A13 A12 A11 A10
command in the SDRAM if the requested transfer size exceeds
ACTV
Chapter 15. Synchronous DRAM Controller Module
A11 A10 A9 A17
11 10 9 17
6 7 8 16
A4 A5 A6 A7
BS2 BS1 BS0
D[23:16] D[15:8] D[7:0]
Byte 1 Byte 2 Byte 3
Byte 1 Driven with
indeterminate values
Byte 3
Driven with
indeterminate values
A6 A7 A8 A9
A9 A17 A18 A19
SDRAM Controller Operation
A19 A21 A23
19 21 23
18 20 22
A8 A9 A10
A10 = CMD BA0 BA1
A20 A21 A22
15-13