Table of Contents
Advertisement
Memory Map and Registers
20.5.18 GPT Port Data Register (GPTPORT)
Field
Reset
R/W
Address
Figure 20-20. GPT Port Data Register (GPTPORT)
Bit(s)
Name
7–4
—
3–0
PORTT
20.5.19 GPT Port Data Direction Register (GPTDDR)
Field
GPT Function
Pulse Accumulator Function
Reset
R/W
Address
Figure 20-21. GPT Port Data Direction Register (GPTDDR)
Bit(s)
Name
7–4
—
3–0
DDRT
20-16
7
6
5
—
IPSBAR + 0x1A_001D, 0x1B_001D
Table 20-21. GPTPORT Field Descriptions
Reserved, should be cleared.
GPT port input capture/output compare data. Data written to GPTPORT is buffered
and drives the pins only when they are configured as general-purpose outputs.
Reading an input (DDR bit = 0) reads the pin state; reading an output (DDR bit = 1)
reads the latched value. Writing to a pin configured as a GPT output does not change
the pin state. These bits are read anytime (read pin state when corresponding
PORTTn bit is 0, read pin driver state when corresponding GPTDDR bit is 1), write
anytime.
7
6
—
—
—
Table 20-22. GPTDDR Field Descriptions
Reserved, should be cleared.
Control the port logic of PORTTn. Reset clears the PORTTn data direction register,
configuring all GPT port pins as inputs. These bits are read anytime, write anytime.
1 Corresponding pin configured as output
0 Corresponding pin configured as input
MCF5282 User's Manual
4
3
PORTT
0000_0000
R/W
Description
5
4
3
PAI
0000_0000
R/W
IPSBAR + 0x1A_001E, 0x1B_001E
Description
0
0
DDRT
IC/OC
—
MOTOROLA
Advertisement
Table of Contents
