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FLASHBAR, 2-8, 6-5
protection (CFMPROT), 6-12
security (CFMSEC), 6-10
supervisor access (CFMSACC), 6-13
user status (CFMUSTAT), 6-15
core
address (An), 2-3
condition code (CCR), 2-4, 2-4
data (Dn), 2-3
stack pointer (A7), 2-3, 2-7
status register (SR), 2-6
vector base (VBR), 2-8
debug
address attribute trigger (AATR), 29-8
address breakpoint (ABLR, ABHR), 29-9
configuration/status (CSR), 29-10
data breakpoint/mask (DBR, DBMR), 29-12
program
counter
(PBR/PBMR), 29-13
trigger definition (TDR), 29-14
DMA controller
byte count (BCRn), 16-7
control (DCRn), 16-8
destination address (DARn), 16-6
request control (DMAREQC), 16-3
source address (SARn), 16-6
status (DSRn), 16-10
DMA timers
capture (DTCRn), 21-7
counters (DTCNn), 21-8
event (DTERn), 21-6
mode (DTMRn), 21-4
reference (DTRRn), 21-7
EMAC
mask (MASK), 3-11
status (MACSR), 3-6
EPORT
data direction (EPDDR), 11-4
flag (EPFR), 11-6
pin assignment (EPPAR), 11-4
pin data (EPPDR), 11-6
port data (EPDR), 11-5
port interrupt enable (EPIER), 11-5
Ethernet
control (ECR), 17-28
descriptor
group
(GAUR/GALR), 17-39
descriptor
individual
(IAUR/IALR), 17-38
descriptor
individual
(IAUR/IALR), 17-37
FIFO receive bound (FRBR), 17-41
FIFO receive start (FRSR), 17-42
FIFO transmit FIFO watermark (TFWR), 17-40
interrupt event (EIR), 17-23
MOTOROLA
INDEX
breakpoint/mask
upper/lower
address
upper/lower
upper/lower
address
MCF5282 User's Manual
interrupt mask (EIMR), 17-26
MIB control (MIBC), 17-32
MII management frame (MMFR), 17-29
MII speed control (MSCR), 17-31
opcode/pause duration (OPD), 17-37
physical address low, 17-35
physical address low/high (PALR, PAUR), 17-35
receive buffer size (EMRBR), 17-44
receive control (RCR), 17-33
receive descriptor active (RDAR), 17-26
receive descriptor ring start (ERDSR), 17-42
registers
transmit
buffer
(ETSDR), 17-43
transmit control (TCR), 17-34
transmit descriptor active (TDAR), 17-27
FEC
physical address low, 17-35
FlexCAN
control 0–2 (CANCTRLn), 25-22–25-25
error and status (ESTAT), 25-28
free running timer (TIMER), 25-26
interrupt flag (IFLAG), 25-31
interrupt mask (IMASK), 25-30
module configuration (CANMCR), 25-20
prescaler divide (PRESDIV), 25-24
receive error counter (RXECTR), 25-32
receive mask (RXGMASK, RXnMASK), 25-27
transmit error counter (TXECTR), 25-32
general purpose timers
channel (GPTCn), 20-13
compare force (GPCFORC), 20-6
control 1–2 (GPTCTLn), 20-9
counter (GPTCNT), 20-7
flag 1–2 (GPTFLGn), 20-12
input
capture/output
(GPTIOS), 20-5
interrupt enable (GPTIE), 20-10
output compare 3 data (GPTOC3D), 20-7
output compare 3 mask (GPTOC3M), 20-6
port data (PORTTn), 20-16
port data direction (GPTDDR), 20-16
pulse accumulator control (GPTPACTL), 20-13
pulse accumulator counter (GPTPACNT), 20-15
pulse accumulator flag (GPTPAFLG), 20-14
system control 1–2 (GPTSCRn), 20-8, 20-11
toggle-on-overflow (GPTTOV), 20-9
GPIO
port AS pin assignment (PASPAR), 26-19
port B/C/D pin assignment (PBCDPAR), 26-14
port clear output data (CLRn), 26-12
port data direction (DDRn), 26-9
port E pin assignment (PEPAR), 26-15
port EH/EL pin assignment (PEHLPAR), 26-20
port F pin assignment (PFPAR), 26-17
descriptor
ring
start
compare
select
Index-11
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