Motorola MPC533 Reference Manual

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MPC533RM/D

4/2003

REV 0

MPC533 Preliminary

Reference Manual

Additional Devices Supported:

MPC534

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

Table of Contents

Summary of Contents for Motorola MPC533

Page 1 MPC533RM/D 4/2003 REV 0 MPC533 Preliminary Reference Manual Additional Devices Supported: MPC534 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 2 Motorola and the Stylized M Logo are registered in the U.S. Patent and Trademark Office. digital dna is a trademark of Motorola, Inc. All other product or service names are the property of their respective owners. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
Page 3: Table Of Contents
1.3.3.4 Queued Serial Multi-Channel Module (QSMCM) ........1-7 1.3.3.5 Peripheral Pin Multiplexing (PPM) ............. 1-8 MPC533 Optional Features ................. 1-8 Comparison of MPC533 and MPC555 ..............1-8 Additional MPC533 Differences ................. 1-9 SRAM Keep-Alive Power Behavior..............1-10 MOTOROLA Contents PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 4: Paragraph
MPC533 Signal Multiplexing................ 2-21 2.2.2 READI Port Signal Sharing................2-22 Pad Module Configuration Register (PDMCR)..........2-23 Pad Module Configuration Register (PDMCR2)..........2-24 MPC533 Development Support Signal Sharing ..........2-25 2.5.1 JTAG Mode Selection..................2-26 Reset State......................2-27 2.6.1 Signal Functionality Configuration Out of Reset .......... 2-27 2.6.2...
Page 5 User Instruction Set Architecture (UISA) ............3-42 3.13.1 Computation Modes..................3-42 3.13.2 Reserved Fields....................3-42 3.13.3 Classes of Instructions ................... 3-43 3.13.4 Exceptions...................... 3-43 3.13.5 Branch Processor ................... 3-43 3.13.6 Instruction Fetching ..................3-43 MOTOROLA Contents PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 6 Instruction Storage Exception (0x0400)............ 3-52 3.15.4.5 External Interrupt (0x0500) ............... 3-52 3.15.4.6 Alignment Exception (0x00600) ............... 3-53 3.15.4.7 Program Exception (0x0700)..............3-55 3.15.4.8 Floating-Point Unavailable Exception (0x0800) ........3-56 3.15.4.9 Decrementer Exception (0x0900).............. 3-57 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 7 DECRAM Standby Operation Mode............4-12 Branch Target Buffer ..................4-12 4.5.1 BTB Operation....................4-13 4.5.1.1 BTB Invalidation ..................4-14 4.5.1.2 BTB Enabling/Disabling ................4-14 4.5.1.3 BTB Inhibit Regions.................. 4-14 BBC Programming Model ................. 4-15 MOTOROLA Contents PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 8 Interrupt Overhead Estimation for Enhanced Interrupt Controller Mode . 6-17 6.1.5 Hardware Bus Monitor .................. 6-18 6.1.6 Decrementer (DEC) ..................6-19 6.1.7 Time Base (TB)....................6-20 6.1.8 Real-Time Clock (RTC)................. 6-21 6.1.9 Periodic Interrupt Timer (PIT)............... 6-21 viii MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 9 Periodic Interrupt Timer Register (PITR)..........6-47 6.2.2.5 General-Purpose I/O Registers ..............6-47 6.2.2.5.1 SGPIO Data Register 1 (SGPIODT1) ..........6-47 6.2.2.5.2 SGPIO Data Register 2 (SGPIODT2) ..........6-48 6.2.2.5.3 SGPIO Control Register (SGPIOCR) ........... 6-49 MOTOROLA Contents PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 10 Internal Clock Signals..................8-7 8.5.1 General System Clocks.................. 8-11 8.5.2 Clock Out (CLKOUT) ................... 8-13 8.5.3 Engineering Clock (ENGCLK) ..............8-14 Clock Source Switching..................8-14 Low-Power Modes..................... 8-16 8.7.1 Entering a Low-Power Mode................. 8-17 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 11 Bus Transfer Signals .................... 9-1 Bus Control Signals ..................... 9-2 Bus Interface Signal Descriptions................ 9-4 Bus Operations..................... 9-8 9.5.1 Basic Transfer Protocol..................9-8 9.5.2 Single Beat Transfer ..................9-9 9.5.2.1 Single Beat Read Flow ................9-9 MOTOROLA Contents PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 12 Show Cycle Transactions................9-57 Chapter 10 Memory Controller 10.1 Overview......................10-1 10.2 Memory Controller Architecture ............... 10-3 10.2.1 Associated Registers ..................10-4 10.2.2 Port Size Configuration ................. 10-5 10.2.3 Write-Protect Configuration ................10-5 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 13 Factory Test Mode ..................11-4 11.5 Data Memory Protection..................11-5 11.5.1 Functional Description................... 11-5 11.5.2 Associated Registers ..................11-7 11.5.3 L-Bus Memory Access Violations..............11-8 11.6 Reservation Support................... 11-8 11.6.1 Reservation Protocol..................11-8 MOTOROLA Contents xiii PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 14 13.2.1 Features of the QADC64E Legacy Mode Operation........13-2 13.2.2 Memory Map ....................13-3 13.2.3 Legacy and Enhanced Modes of Operation........... 13-4 13.2.4 Using the Queue and Result Word Table............13-5 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 15 Software Initiated Single-Scan Mode..........13-42 13.5.4.3.2 External Trigger Single-Scan Mode ............ 13-42 13.5.4.3.3 External Gated Single-Scan Mode ............13-43 13.5.4.3.4 Periodic/Interval Timer Single-Scan Mode ......... 13-43 13.5.4.4 Continuous-Scan Modes................13-44 13.5.4.4.1 Software Initiated Continuous-Scan Mode.......... 13-45 MOTOROLA Contents PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 16 Switching Between Legacy and Enhanced Modes of Operation..... 14-10 14.3.1.4 Supervisor/Unrestricted Address Space ..........14-11 14.3.2 QADC64E Interrupt Register ..............14-12 14.3.3 Port Data Register..................14-14 14.3.4 Port Data Direction Register................ 14-14 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 17 14.5.7.1 QADC64E Bus Interface Unit ..............14-53 14.5.7.2 QADC64E Bus Accessing ............... 14-53 14.6 Trigger and Queue Interaction Examples ............14-55 14.6.1 Queue Priority Schemes................14-55 14.6.2 Conversion Timing Schemes ............... 14-65 MOTOROLA Contents xvii PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 18 Accommodating Positive/Negative Stress Conditions ......14-78 Chapter 15 Queued Serial Multi-Channel Module 15.1 Block Diagram ....................15-1 15.2 Key Features ...................... 15-2 15.2.1 MPC533 QSMCM Details................15-4 15.3 Memory Maps....................15-4 15.4 QSMCM Global Registers................. 15-6 15.4.1 Low-Power Stop Operation ................15-6 15.4.2 Freeze Operation....................
Page 19 Receiver Wake-Up................... 15-63 15.7.7.11 Internal Loop Mode ................. 15-63 15.8 SCI Queue Operation..................15-63 15.8.1 Queue Operation of SCI1 for Transmit and Receive........15-63 15.8.2 Queued SCI1 Status and Control Registers ..........15-64 MOTOROLA Contents PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 20 Transmit Message Buffer Deactivation ........... 16-15 16.4.3.2 Reception of Transmitted Frames............16-15 16.4.4 Receive Process ................... 16-15 16.4.4.1 Receive Message Buffer Deactivation............. 16-16 16.4.4.2 Locking and Releasing Message Buffers..........16-17 16.4.5 Remote Frames .................... 16-18 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 21 MIOS14 Programmer’s Model ................ 17-10 17.4.1 Bus Error Support ..................17-10 17.4.2 Wait States ....................17-11 17.5 MIOS14 I/O Ports .................... 17-11 17.6 MIOS14 Bus Interface Submodule (MBISM)..........17-11 17.6.1 MIOS14 Bus Interface (MBISM) Registers ..........17-11 MOTOROLA Contents PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 22 Output Port Bit Operation................ 17-35 17.9.5.5 Output Pulse Width Modulation (OPWM) Mode........17-35 17.9.6 Modular I/O Bus (MIOB) Interface............. 17-38 17.9.7 Effect of RESET on MDASM ..............17-39 17.9.8 MDASM Registers ..................17-39 xxii MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 23 17.11.6 MPIOSM Testing..................17-62 17.11.7 MPIOSM Registers..................17-62 17.11.8 MPIOSM Register Organization ..............17-62 17.11.8.1 MPIOSM Data Register (MPIOSMDR)..........17-63 17.11.8.2 MPIOSM Data Direction Register (MPIOSMDDR)....... 17-63 17.12 MIOS14 Interrupts ................... 17-63 MOTOROLA Contents xxiii PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 24 Entering Stop Mode................. 18-10 18.4.2 PPM Control Register (PPMPCR)............... 18-11 18.4.3 Transmit Configuration Registers (TX_CONFIG_1 and TX_CONFIG_2) 18-14 18.4.4 Receive Configuration Registers (RX_CONFIG_1 and RX_CONFIG_2). 18-15 18.4.5 Receive Data Register (RX_DATA) ............18-16 xxiv MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 25 Program Shadow Information..............19-24 19.3.7.3 Program Suspend ..................19-25 19.3.8 Erasing ......................19-25 19.3.8.1 Erase Sequence ..................19-26 19.3.8.2 Erasing Shadow Information Words............19-28 19.3.8.3 Erase Suspend..................19-28 19.3.9 Stop Operation ..................... 19-29 MOTOROLA Contents PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 26 History Buffer Flushes Status Pins— VFLS [0:1] ........21-4 21.1.1.3 Queue Flush Information Special Case ............. 21-4 21.1.2 Program Trace when in Debug Mode............21-4 21.1.3 Sequential Instructions Marked as Indirect Branch........21-5 xxvi MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 27 Development Serial Data Out ..............21-35 21.4.5 Freeze Signal....................21-36 21.4.5.1 SGPIO6/FRZ/PTR Signal ................ 21-36 21.4.5.2 IWP[0:1]/VFLS[0:1] Signals..............21-36 21.4.5.3 VFLS[0:1]/MPIO32B[3:4] Signals ............21-36 21.4.6 Development Port Registers ................ 21-36 21.4.6.1 Development Port Shift Register ............. 21-36 MOTOROLA Contents xxvii PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 28 Security ...................... 22-4 22.0.3.3 Normal ....................... 22-4 22.0.3.4 Disabled ..................... 22-4 22.0.4 Parametrics..................... 22-4 22.0.5 Programming Model ..................22-5 22.0.6 Messages......................22-5 22.0.7 Terms and Definitions..................22-7 22.1 Programming Model ..................22-8 xxviii MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 29 Disabled Mode..................22-38 22.2.3.5 Guidelines For Transmitting Input Messages .......... 22-39 22.3 Program Trace....................22-39 22.3.1 Branch Trace Messaging................22-39 22.3.1.1 RCPU Instructions that Cause BTM Messages ........22-40 22.3.2 BTM Message Formats................22-40 MOTOROLA Contents xxix PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 30 Assumptions for Throughput Analysis............ 22-61 22.4.8.2 Throughput Calculations ................. 22-61 22.4.9 Data Timing Diagrams................. 22-62 22.5 Read/Write Access................... 22-63 22.5.1 Functional Description................. 22-63 22.5.2 Write Operation to Memory-Mapped Locations and MPC500 Registers ... 22-66 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 31 RCPU Development Access Messaging............22-82 22.9.1.1 DSDI Message ..................22-82 22.9.1.2 DSDO Message ..................22-83 22.9.1.3 BDM Status Message ................22-83 22.9.1.4 Error Message (Invalid Message)............22-84 22.9.2 RCPU Development Access Operation ............22-84 MOTOROLA Contents xxxi PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 32 Compressed Address Generation– Exceptions ..........A-7 A.2.7 Class Code Compression Algorithm Rules ............ A-8 A.2.8 Bypass Field Compression Rules ..............A-8 A.2.8.1 Branch Right Segment Compression #1............. A-9 A.2.8.2 Branch Right Segment Compression #2............. A-9 xxxii MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 33 Crystal Oscillator External Components .............C-3 C.3.1 KAPWR Filtering ....................C-4 C.3.2 PLL External Components................C-5 C.3.3 PLL Off-Chip Capacitor CXFC...............C-5 PLL and Clock Oscillator External Components Layout Requirements .....C-6 C.4.1 Traces and Placement ..................C-6 C.4.2 Grounding/Guarding..................C-6 MOTOROLA Contents xxxiii PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 34 MPWMSM Timing Characteristics ...............E-63 E.18.2 MMCSM Timing Characteristics ..............E-65 E.18.3 MDASM Timing Characteristics ..............E-67 E.19 MPIOSM Timing Characteristics ..............E-70 E.20 Pin Summary .....................E-71 E.20.1 Package Diagrams..................E-71 E.21 MPC533 Pinout Diagram...................E-74 xxxiv MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 35 Title Number MPC533 Block Diagram..................... 1-3 Recommended Connection Diagram for IRAMSTBY..........1-11 MPC533 Memory Map ..................... 1-12 MPC533 Internal Memory Map................1-13 MPC533 Signal Groupings ..................2-2 Pads Module Configuration Register (PDMCR) ............2-23 Pads Module Configuration Register 2 (PDMCR2) ..........2-25 RCPU Block Diagram....................
Page 36 Circuit Paths of Reading and Writing to SGPIO............6-8 MPC533 Interrupt Structure..................6-9 Lower Priority Request Masking—One Bit Diagram..........6-14 MPC533 Interrupt Controller Block Diagram ............6-16 Typical Interrupt Handler Routine ................6-18 RTC Block Diagram....................6-21 PIT Block Diagram ....................6-22 SWT State Diagram ....................
Page 37 General System Clocks Select .................. 8-11 Divided System Clocks Timing Diagram ..............8-12 Clocks Timing For DFNH = 1 (or DFNL = 0)............8-13 Clock Source Switching Flow Chart................. 8-15 MPC533 Low-Power Modes Flow Diagram ............8-21 8-10 Basic Power Supply Configuration................8-23 8-11 External Power Supply Scheme ................
Page 38 9-37 Peripheral Mode: External Master Reads from – Two Wait States......9-54 9-38 Peripheral Mode: External Master Writes to MPC533 — Two Wait States ................9-55 9-39 Flow of Retry of External Master Read Access............9-56 9-40 Retry of External Master Access (Internal Arbiter)..........9-57 9-41 Instruction Show Cycle Transaction .................
Page 39 IMB Clock – Full-Speed IMB Bus ................12-3 12-3 IMB Clock – Half-Speed IMB Bus................12-3 12-4 Interrupt Synchronizer Signal Flow ................12-4 12-5 Time-Multiplexing Protocol for IRQ Signals ............12-5 12-6 Interrupt Synchronizer Block Diagram..............12-7 MOTOROLA Figures xxxix PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 40 CCW Priority Situation 11 ..................13-61 13-36 CCW Freeze Situation 12 ..................13-62 13-37 CCW Freeze Situation 13 ..................13-62 13-38 CCW Freeze Situation 14 ..................13-62 13-39 CCW Freeze Situation 15 ..................13-63 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 41 QADC64E Clock Subsystem Functions ..............14-51 14-23 Bus Cycle Accesses ....................14-54 14-24 CCW Priority Situation 1..................14-57 14-25 CCW Priority Situation 2..................14-58 14-26 CCW Priority Situation 3..................14-58 14-27 CCW Priority Situation 4..................14-59 MOTOROLA Figures PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 42 SPCR1 — QSPI Control Register................15-20 15-13 SPCR2 — QSPI Control Register 2................ 15-21 15-14 SPCR3 — QSPI Control Register 3................ 15-21 15-15 QSPI Status Register (SPSR).................. 15-22 15-16 QSPI RAM ......................15-24 xlii MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 43 Control Register 1 (CANCTRL1)................16-30 16-13 Prescaler Divide Register..................16-31 16-14 Control Register 2 (CANCTRL2)................16-32 16-15 Free Running Timer Register (TIMER)..............16-32 16-16 Receive Global Mask Register: High (RXGMSKHI), Low (RXGMSKLO) ..16-33 MOTOROLA Figures xliii PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 44 Interrupt Flag Register (IFLAG)................16-38 16-22 Receive Error Counter (RXECTR), Transmit Error Counter (TXECTR) ....16-38 17-1 MPC533 MIOS14 Block Diagram................17-2 17-2 The MIOS14 does not generate wait states.MIOS14 Memory Map....... 17-11 17-3 Test and Signal Control Register (MIOS14TPCR)..........17-12 17-4 Vector Register (MIOS14VECT)................
Page 45 Scale Transmit Clock Register ......... (SCALE_TCLK_REG)18-21 19-1 UC3F EEPROM Configuration Register (UC3FMCR)..........19-5 19-2 UC3FMCRE— UC3F EEPROM Extended Configuration Register......19-8 19-3 UC3F EEPROM High Voltage Control Register (UC3FCTL) ....... 19-11 19-4 PEGOOD Valid Time....................19-14 MOTOROLA Figures PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 46 Erase State Diagram....................19-27 19-10 Censorship States and Transitions ................19-34 20-1 System Block Diagram ..................... 20-2 20-2 MPC533 Memory Map with CALRAM Address Ranges ........20-2 20-3 Standby Power Supply Configuration for CALRAM Array ........20-2 20-4 CALRAM Array ....................... 20-5 20-5 CALRAM Module Overlay Map of Flash (CLPS = 1) ..........
Page 47 Program Trace Full Message Format ..............22-49 22-32 Relative Address Generation and Re-Creation ............22-50 22-33 Error Message (Queue Overflow) Format .............. 22-50 22-34 Direct Branch Message ................... 22-52 22-35 Indirect Branch Message..................22-52 MOTOROLA Figures xlvii PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 48 Error Message (Watchpoint Overrun) Format ............22-79 22-71 Watchpoint Message ....................22-79 22-72 Error Message (Watchpoint Overrun) ..............22-79 22-73 Ownership Trace Message Format................22-80 22-74 Error Message Format..................... 22-80 xlviii MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 49 Decompressor Class Configuration Registers1........(DCCR0–15)A-24 Power Distribution Diagram — 5 V and Analog............C-2 Crystal Oscillator Circuit ....................C-3 RC Filter Example ......................C-4 Bypass Capacitors Example (Alternative) ..............C-4 RC Filter Example ......................C-5 LC Filter Example (Alternative) .................C-5 MOTOROLA Figures xlix PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 50 Debug Port Timings ....................E-45 K-30 Auxiliary Port Data Input Timing Diagram ..............E-46 K-31 Auxiliary Port Data Output Timing Diagram ............E-47 K-32 Enable Auxiliary From RSTI ..................E-47 K-33 Disable Auxiliary From RSTI...................E-47 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 51 Counter Bus to MDASM Interrupt Flag Setting Timing Diagram ......E-69 K-60 MPIOSM Input Pin to MPIOSM_DR (Data Register) Timing Diagram ....E-70 K-61 MPC533 Package Footprint (1 of 2) .................E-72 K-62 MPC533 Package Footprint (2 of 2) .................E-73 K-63 MPC533 Pinout Diagram..................E-75...
Page 52 Figures Figure Page Number Title Number MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 53 Number Notational Conventions.................... lxxiii Acronyms and Abbreviated Terms................lxxiii MPC533/MPC534 Features ..................1-1 Differences Between MPC555 and MPC533 ............. 1-9 MPC533 Signal Descriptions..................2-3 MPC533 Signal Sharing.................... 2-21 Reduced and Full Port Mode Pads ................2-22 Full Port Only Mode Pads..................2-23 PDMCR Field Descriptions ..................
Page 54 General Pins Configuration..................6-28 6-10 Single-Chip Select Field Pin Configuration.............. 6-28 6-11 Multi-Level Reservation Control Pin Configuration ..........6-29 6-12 IMMR Bit Descriptions ................... 6-30 6-13 EMCR Bit Descriptions ................... 6-31 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 55 COLIR Bit Descriptions................... 8-36 8-13 VSRMCR Bit Descriptions ..................8-37 MPC533 SIU Signals ....................9-4 Data Bus Requirements For Read Cycles ..............9-31 Data Bus Contents for Write Cycles ................. 9-32 Priority Between Internal and External Masters over External Bus ......9-36 4 Word Burst Length and Order................
Page 56 QACR2 Bit Descriptions ..................13-16 13-8 Queue 2 Operating Modes ..................13-17 13-9 QASR0 Bit Descriptions ..................13-20 13-10 Pause Response ....................... 13-23 13-11 Queue Status ......................13-24 13-12 QASR1 Bit Descriptions ..................13-26 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 57 Effect of DDRQS on QSPI Pin Function..............15-11 15-9 QSMCM Pin Functions................... 15-13 15-10 PQSPAR Bit Descriptions..................15-13 15-11 DDRQS Bit Descriptions ..................15-14 15-12 QSPI Register Map ....................15-17 15-13 SPCR0 Bit Descriptions..................15-19 MOTOROLA Tables lvii PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 58 PRESDIV Bit Descriptions ..................16-31 16-18 CANCTRL2 Bit Descriptions ................16-32 16-19 TIMER Bit Descriptions ..................16-33 16-20 RXGMSKHI, RXGMSKLO Bit Descriptions............16-33 16-21 RX14MSKHI, RX14MSKLO Field Descriptions ..........16-34 lviii MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 59 MPWMPERR Bit Descriptions ................17-57 17-28 MPWMPULR Bit Descriptions ................17-57 17-29 MPWMCNTR Bit Descriptions................17-58 17-30 MPWMSCR Bit Descriptions ................. 17-58 17-31 PWMSM Output Signal Polarity Selection ............17-59 17-32 Prescaler Values ...................... 17-60 MOTOROLA Tables PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 60 20-4 RGN_SIZE Encoding ..................... 20-11 20-5 CRAMOVLCR Bit Descriptions ................20-12 21-1 VF Pins Instruction Encodings ................. 21-3 21-2 VF Pins Queue Flush Encodings ................21-4 21-3 VFLS Pin Encodings....................21-4 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 61 22-8 RCPU Development Access Modes ............... 22-11 22-9 MC Bit Descriptions ....................22-12 22-10 UBA Bit Descriptions ..................... 22-13 22-11 RWA Read/Write Access Bit Descriptions ............. 22-14 22-12 UDI Bit Descriptions ....................22-16 MOTOROLA Tables PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 62 QSMCM A and B (Queued Serial Multi-Channel Module) ........B-11 H-11 MIOS14 (Modular Input/Output Subsystem) ............B-14 H-12 TouCAN B (CAN 2.0B Controller) ................B-22 H-13 UIMB (U-Bus to IMB Bus Interface) ...............B-24 lxii MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 63 K-18 QSCI Timing ......................E-58 K-19 TouCAN Timing .......................E-61 K-20 MCPSM Timing Characteristics ................E-62 K-21 MPWMSM Timing Characteristics ................E-63 K-22 MMCSM Timing Characteristics................E-65 K-23 MDASM Timing Characteristics ................E-67 K-24 MPIOSM Timing Characteristics ................E-70 MOTOROLA Tables lxiii PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 64 Tables Table Page Number Title Number lxiv MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 65: About This Book
Appendix G, “MPC534 Compression Features.” Audience This manual is intended for system software and hardware developers and applications programmers who want to develop products for the MPC533. It is assumed that the reader understands operating systems, and microprocessor and microcontroller system design. Organization Following is a summary and brief description of the major sections of this manual: •...
Page 66 • Chapter 8, “Clocks and Power Control.” The main timing and power control reference for the MPC533. • Chapter 9, “External Bus Interface,” The MPC533 external bus is a synchronous, burstable bus. Signals driven on this bus must adhere to the setup and hold time relative to the bus clock’s rising edge.
Page 67 (SCI/UART). These submodules communicate with the CPU via a common slave bus interface unit (SBIU). • Chapter 16, “CAN 2.0B Controller Module.” The MPC533 contains one CAN 2.0B controller modules (TouCAN A). TouCAN A is a communication controller that implements the Controller Area Network (CAN) protocol, an asynchronous communications protocol used in automotive and industrial control systems.
Page 68: Suggested Reading
• Appendix K, “Electrical Characteristics,” contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing characteristics of the MPC533. The MPC533 is designed to operate at 40 MHz, or optionally up to 56 MHz. • Appendix G, “MPC534 Compression Features,” includes information about code compression features of the MPC534.
Page 69: Conventions And Nomenclature
Second Edition, by International Business Machines, Inc. For updates to the specification, see http://www.austin.ibm.com/tech/ppc-chg.html. Motorola documentation is available from the sources listed on the back cover of this manual; the document order numbers are included in parentheses for ease in ordering: •...
Page 70 The only exceptions to this appear in the discussion of serial communication modules that support variable-length data transmission units. To simplify the discussion these units are referred to as words regardless of length. MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 71: Notational Conventions
Acronyms and Abbreviations Table ii contains acronyms and abbreviations that are used in this document. Table ii. Acronyms and Abbreviated Terms Term Meaning Arithmetic logic unit BIST Built-in self test MOTOROLA About This Book lxxi PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 72 No operation Operating environment architecture Phase-locked loop Power-on reset Processor version register RISC Reduced instruction set computing Special-purpose register SRR0 Machine status save/restore register 0 SRR1 Machine status save/restore register 1 lxxii MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 73: References
It is recommended to use the Sematech Official Dictionary and the Reference Guide to Letter Symbols for Semiconductor Devices by the JEDEC Council/Electronics Industries Association as references for terminology and symbology. MOTOROLA About This Book lxxiii PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 74 References lxxiv MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 75: Overview
MPC533 MPC533 and MPC534 members of the Motorola MPC500 RISC Microcontroller family. Unless otherwise noted, references to the MPC533 also includes the MPC534. Any functional differences between the MPC533 and MPC534 are noted. Table 1-1. MPC533/MPC534 Features Device...
Page 76: Block Diagram
— 2.6 ± 0.1-V external bus with a 5-V tolerant I/O system — 2.6 ± 0.1-V internal logic — IRAMSTBY on-chip voltage regulator Block Diagram Figure 1-1 is a block diagram of the MPC533. MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 77: Key Features
IMB3 MIOS14 QADC64E Figure 1-1. MPC533 Block Diagram Key Features The MPC533 key features are explained in the following sections. 1.3.1 High Performance CPU System • Fully static design • Four major power saving modes — On, doze, sleep, deep-sleep, and power-down 1.3.1.1...
Page 78: Mpc5Xx System Interface (Usiu)
• Support for enhanced exception table relocation feature • Branch target buffer • Contains 2 Kbytes of decompression RAM (DECRAM) for code compression. This RAM may also be used as general-purpose RAM when code compression feature not used. MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 79: Flexible Memory Protection Unit
— 4-Kbyte calibration (overlay) RAM feature that allows calibration of flash-based constants • Eight 512-byte overlay regions • One clock fast accesses • Two clock cycle access option for power saving • Keep-alive power (IRAMSTBY) for data retention MOTOROLA Chapter 1. Overview PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 80: General Purpose I/O Support (Gpio)
• Up to 41 total input channels on the QADC64E module with external multiplexing • Software configurable to operate in enhanced or legacy (MPC555 compatible) mode • Unused analog channels can be used as digital input/output signals MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 81: One Can 2.0B Controller (Toucan) Module
— Synchronous serial interface with baud rate of up to system clock / 4 — Four programmable peripheral-selects signals: — Support up to 16 devices with external decoding — Support up to eight devices with internal decoding MOTOROLA Chapter 1. Overview PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 82: Peripheral Pin Multiplexing (Ppm)
— Start-transmit-receive (STR) mode • Software configurable internal modules interconnect (shorting) MPC533 Optional Features The following features of the MPC533 are optional features and may not appear in certain configurations: • Code compression on MPC534 Comparison of MPC533 and MPC555 In Table 1-2, the MPC555 is used as a baseline to compare the high level differences from an early device offering in the MPC500 family to the MPC533.
Page 83: Additional Mpc533 Differences
— New Module Additional MPC533 Differences • The MPC533 is very similar to the MPC555 with the following differences: — CDR3 technology — Two power supplies: 5.0-V I/O, 2.6-V external bus signals, 2.6-V internal logic — New modules: READI, CALRAM, PPM —...
Page 84: Sram Keep-Alive Power Behavior
One keep-alive power pin (IRAMSTBY) provides keep-alive power to RAM. The IRAMSTBY pin can be powered directly from a battery using an internal shunt regulator or via a small battery for standby use. See Figure 1-2. 1-10 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 85: Mpc533 Address Map
MPC533 Address Map To Battery To IRAMSTBY Pad Figure 1-2. Recommended Connection Diagram for IRAMSTBY While power is off to the MPC533, the IRAMSTBY supply powers the following: • 32-Kbyte CALRAM • 2-Kbyte BBC DECRAM module MPC533 Address Map The internal memory map is organized as a single 4-Mbyte block. The user can assign this block to one of eight locations by programming a register in the USIU (IMMR[ISB]).
Page 86 0x01BF FFFF 0x01C0 0000 0x01FF FFFF 0xFFFF FFFF Figure 1-3. MPC533 Memory Map The internal memory space is divided into the following sections. Refer to Figure 1-4. • Flash memory (512-Kbytes) • CALRAM static RAM memory (32-Kbytes) • Control registers and IMB3 modules (64 Kbytes) —...
Page 87: Supporting Documentation List
*NOTE: Reserved, do not write to this space. 0x30 7F80 UIMB Registers (128 bytes) 0x30 7FFF Figure 1-4. MPC533 Internal Memory Map Supporting Documentation List This list contains references to currently available and planned documentation. MOTOROLA Chapter 1. Overview 1-13...
Page 88 Supporting Documentation List • MPC555 User’s Manual (MPC555UM/AD) • RCPU Reference Manual (RCPURM/AD) • Nexus Standard Specification (non-Motorola document) • Nexus Web Site: http://www.nexus5001.org • IEEE 1149.1 Specification (non-Motorola document) 1-14 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 89: Signal Descriptions
DATA0, DATA1, and so forth. Refer to Appendix E, “Electrical Characteristics,” for detailed electrical information for each signal. Signal Groupings Figure 25-1 shows the external signals of the MPC533 grouped by functional module (pad area). MOTOROLA Chapter 2. Signal Descriptions...
Page 90 Note: In cases where one multiplexed signal QVDDL is an input and another is an output, together KAPWR they are shown as I/O. VDDH NVDDL Global Power Supply Figure 2-1. MPC533 Signal Groupings MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 91: Signal Summary
Signal Summary Signal Summary Table 25-1 describes individual MPC533 signals, grouped by functional module. Table 2-1. MPC533 Signal Descriptions No. of Function Signal Name Type Description Signals after Reset Bus Interface Address Bus [8:31] – Specifies the physical address of the Controlled by bus transaction.
Page 92 MPC533. Output Enable – This output line is asserted when a read access is initiated by the MPC533 to an external slave controlled by the memory controller’s GPCM. RSTCONF Reset Configuration –...
Page 93 RCPU. Cancel Reservation – Instructs the MPC533 to clear its reservation because some other master has touched its reserved space. An external bus snooper asserts this...
Page 94 Signal Summary Table 2-1. MPC533 Signal Descriptions (continued) No. of Function Signal Name Type Description Signals after Reset Interrupt Request 4 – One of the eight external signals that can request, by means of the internal interrupt controller, a service routine from the RCPU.
Page 95 MPC533. It can be optionally asserted on all read and write accesses. See WEBS bit definition in Table 33-9. WEn/BEn are asserted when data lanes shown below contain valid data to be stored by the slave device.
Page 96 Controlled by Visible Instruction Queue Flush Status 0 – This output RCW[DBGC] signal together with VF1 and VF2 is output by the MPC533 BG / VF0 / LWP1 when program instruction flow tracking is required. VFs Table 29-8.
Page 97 Visible Instruction Queue Flush Status 2 – This output Controlled by signal together with VF0 and VF1 is output by the MPC533 RCW[DBGC] when a program instructions flow tracking is required. VFs BB / VF2 / IWP3...
Page 98 CQDS bits in the SCCR register in the USIU. EXTCLK EXTCLK EXTCLK – Input. This is the external frequency source for the MPC533. If EXTCLK is unused, it must be grounded. 2-10 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 99 2.6 V, 5 V (with slew-rate control), or disabled. The drive voltage is configured using the EECLK[0:1] bits in the SCCR register in the SIU. BUCLK – When the MPC533 is in limp mode, it is operating ENGCLK / BUCLK ENGCLK from a less precise on-chip ring oscillator to allow the (2.6 V)
Page 100 Signal Summary Table 2-1. MPC533 Signal Descriptions (continued) No. of Function Signal Name Type Description Signals after Reset ETRIG [1:2] – These are the external trigger inputs to the QADC64E_A module. ETRIG1 can be configured to be used by both QADC64E_A . Likewise, ETRIG2 can be used by QADC64E_A.
Page 101 Signal Summary Table 2-1. MPC533 Signal Descriptions (continued) No. of Function Signal Name Type Description Signals after Reset Analog Input [52:54] – Input-only. These inputs are passed on as separate signals to the QADC64E. Multiplexed Address [0:2] for QADC64E Module A–...
Page 102 Signal Summary Table 2-1. MPC533 Signal Descriptions (continued) No. of Function Signal Name Type Description Signals after Reset Analog Input 3 – Internally multiplexed input-only analog channel. The input is passed on as a separate signal to the QADC64E. Multiplexed Analog Input (B_ANz) – Externally multiplexed...
Page 103 Signal Summary Table 2-1. MPC533 Signal Descriptions (continued) No. of Function Signal Name Type Description Signals after Reset PCS0 – This signal provides QSPI peripheral chip select 0 for the QSMCM module. SS– Assertion of this bidirectional signal places the QSPI QGPIO0 in slave mode.
Page 104 Signal Summary Table 2-1. MPC533 Signal Descriptions (continued) No. of Function Signal Name Type Description Signals after Reset Transmit Data 2 – This is the serial data output from the SCI1 TXD2 / QGPO2 QGPO2 Port QSCI GPO 2 – When this signal is not needed for a SCI applications it can be configured as general-purpose output.
Page 105 Signal Summary Table 2-1. MPC533 Signal Descriptions (continued) No. of Function Signal Name Type Description Signals after Reset MPWM[1] Pulse Width Modulation 1 – This signal provides a variable unless the pulse width output signal at a wide range of frequencies.
Page 106 MIOS14 GPIO 0 – Allows the signals to be used as general-purpose inputs/outputs. Visible Instruction Queue Flush Status 0 – These signals MPIO32B[0] output by the MPC533 when program instruction flow unless the tracking is required. VF reports the number of instructions Nexus flushed from the instruction queue in the internal core.
Page 107 MIOS14 GPIO 3 – Allows the signal to be used as a general-purpose input/output. Visible History Buffer Flush Status 0 – This signal is output MPIO32B3 by the MPC533 to allow program instruction flow tracking. unless the It reports the number of instructions flushed from the Nexus history buffer in the RCPU.
Page 108 Signal Summary Table 2-1. MPC533 Signal Descriptions (continued) No. of Function Signal Name Type Description Signals after Reset MIOS14 GPIO 11 – This function allows the signals to be used as a general-purpose inputs/outputs. MPIO32B11 / C_CNRX0 MPIO32B11 TOUCAN_C Receive – This signal is the serial data input to the TOUCAN_C module.
Page 109: Mpc533 Signal Multiplexing
The input applies only in legacy mode. 2.2.1 MPC533 Signal Multiplexing Table 25-2 describes the signal multiplexing that occurs between different modules of the MPC533. Most of the signal functions are controlled by the PDMCR2 register. Table 2-2. MPC533 Signal Sharing Signal Name Module Sharing...
Page 110: Pad Module Configuration Register (Pdmcr)
Bits in the PDMCR (which resides in the SIU memory map) control the slew rate and weak pull-up/pull-down characteristics of some signals; refer to Appendix E, “Electrical Characteristics.” The PORESET/TRST signal resets all the PDMCR bits asynchronously. 2-22 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 111 Signals affected by the PRDS bit include the following: • all SGPIO signals 0 Enable weak pull-up/pull down devices on pads controlled by this signal. 1 Disable weak pull-up/pull down devices on pads controlled by this signal. MOTOROLA Chapter 2. Signal Descriptions 2-23 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 112: Pad Module Configuration Register (Pdmcr2)
Table 25-10. MPC533 Development Support Signal Sharing On the MPC533, the JTAG, BDM, and READI (Nexus interface) signals are all shared. Only one set of signals can be active at a time. Table 2-6 shows the shared functions in the different modes.
Page 113: Jtag Mode Selection
2.5.1 JTAG Mode Selection The MPC533 has five JTAG signals. The test data input (TDI) and test data output (TDO) scan ports are used to scan instructions as well as data into the various scan registers for JTAG operations. The scan operation is controlled by the test access port (TAP) controller, which in turn is controlled by the test mode select (TMS) input sequence.
Page 114: Reset State
To prevent these conditions, the signals need to have a defined reset state. Table 25-15 describes the reset state of the signals based on signal functionality. 2-26 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 115: Power-On Reset And Hard Reset
PDMCR register. When this bit is negated, the pull-down is enabled, when asserted the pull-down will be disabled. NOTE All pull-up/pull-down devices are disabled when all the signals are forced to three state in JTAG mode. MOTOROLA Chapter 2. Signal Descriptions 2-27 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 116: Special Pull Resistor Disable Control Functionality (Sprds)
2.6-V outputs to a driver or pull-up greater than 3.1 V. NOTE Depending on the application, pins may require a pull-down resistor to avoid getting any command due to noise. 2-28 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 117: Central Processing Unit
This section provides an overview of the RCPU. For a detailed description of this processor, refer to the RCPU Reference Manual. The following sections describe each block and sub-block. MOTOROLA Chapter 3. Central Processing Unit PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 118: Rcpu Block Diagram
Sequencer ALU/ Instruction Pre-fetch IMUL/ Queue IDIV I-DATA History Branch Processor Unit (32 X 32) I-ADDR Next Address Control Generation Regs Write Back Bus 2 slots/clock Figure 3-1. RCPU Block Diagram MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 119: Rcpu Key Features
The BPU extracts branch instructions from the pre-fetch queue and, using branch prediction on unresolved conditional branches, allows the instruction sequencer to fetch instructions from a predicted target stream while a conditional branch is MOTOROLA Chapter 3. Central Processing Unit PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 120: Independent Execution Units
For example, since branch instructions do not depend on GPRs, branches can often be resolved early, eliminating stalls caused by taken branches. MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 121: Branch Processing Unit (Bpu)
The CR bits indicate conditions that may result from the execution of relevant instructions. MOTOROLA Chapter 3. Central Processing Unit PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 122: Integer Unit (Iu)
Addresses are formed by adding the source-one register operand specified by the instruction (or zero) to either a source-two register operand or to a 16-bit, immediate value embedded in the instruction. MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 123: Floating-Point Unit (Fpu)
Floating-Point Unit (FPU) The FPU contains a double-precision multiply array, the floating-point status and control register (FPSCR), and the FPRs. The multiply-add array allows the MPC533 to efficiently implement floating-point operations such as multiply, multiply-add, and divide. The MPC533 depends on a software envelope to fully implement the IEEE floating-point specification.
Page 124: Rcpu Programming Model
(mtspr) or move from special-purpose register (mftspr), or implicitly as part of an instruction’s execution. Some registers are accessed both explicitly and implicitly. MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 125 Link Register (LR) Count Register (CTR) USER MODEL VEA Time Base Facility (for Reading) Time Base Lower – Read (TBL) Time Base Upper – Read (TBU) Figure 3-3. RCPU Programming Model MOTOROLA Chapter 3. Central Processing Unit PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 126 RCPU Programming Model Table 3-2 lists the MPC533 supervisor-level registers. Table 3-2. Supervisor-Level SPRs SPR Number Special-Purpose Register (Decimal) DAE/Source Instruction Service Register (DSISR) See Section 3.9.2, “DAE/Source Instruction Service Register (DSISR),” for bit descriptions. Data Address Register (DAR) See Section 3.9.3, “Data Address Register (DAR),” for bit descriptions.
Page 127 See Table 11-9 for bit descriptions. L2U Region Attribute Register 1 (L2U_RA1) See Table 11-9 for bit descriptions. L2U Region Attribute Register 2 (L2U_RA2) See Table 11-9 for bit descriptions. MOTOROLA Chapter 3. Central Processing Unit 3-11 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 128 1022 Floating-Point Exception Cause Register (FPECR) See Section 3.9.10.2, “Floating-Point Exception Cause Register (FPECR),” for bit descriptions. Implementation-specific SPR. Table 3-3 lists the MPC533 SPRs used for development support. Table 3-3. Development Support SPRs SPR Number Special-Purpose Register (Decimal) Comparator A Value Register (CMPA) See Table 21-20 for bit descriptions.
Page 129: User Instruction Set Architecture (Uisa) Register Set
Figure 3-4. General-Purpose Registers (GPRs) 3.7.2 Floating-Point Registers (FPRs) The MPC500 architecture provides 32 64-bit FPRs. These registers are accessed as source and destination registers through operands in floating-point instructions. Each FPR MOTOROLA Chapter 3. Central Processing Unit 3-13 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 130: Floating-Point Status And Control Register (Fpscr)
Table 3-4 summarizes which bits in the FPSCR are sticky status bits, which are normal status bits, and which are control bits. Table 3-4. FPSCR Bit Categories Bits Type [0], [3:12], [21:23] Status, sticky [1:2], [13:20] Status, not sticky [24:31] Control 3-14 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 131 Floating-point invalid operation exception for ∞ - ∞. VXISI Sticky bit Floating-point invalid operation exception for ∞/∞. VXIDI Sticky bit VXZDZ Floating-point invalid operation exception for 0/0. Sticky bit MOTOROLA Chapter 3. Central Processing Unit 3-15 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 132 Floating-point underflow exception enable. This bit should not be used to — determine whether denormalization should be performed on floating-point stores. Floating-point zero divide exception enable. — Floating-point inexact exception enable. — 3-16 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 133: Condition Register (Cr)
• Specified fields of the CR can be set by an instruction (mtcrf) to move to the CR from a GPR. • Specified fields of the CR can be moved from one CRx field to another with the mcrf instruction. MOTOROLA Chapter 3. Central Processing Unit 3-17 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 134: Condition Register Cr0 Field Definition
Floating-point exception (FX). This is a copy of the final state of FPSCR[FX] at the completion of the instruction. Floating-point enabled exception (FEX).This is a copy of the final state of FPSCR[FEX] at the completion of the instruction. 3-18 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 135: Condition Register Crn Field - Compare Instruction
For example, the result of the subtract from carrying (subfcx) instruction is specified as the sum of three values. This instruction sets bits in the XER based on the entire operation, not on an intermediate sum. MOTOROLA Chapter 3. Central Processing Unit 3-19...
Page 136: Link Register (Lr)
4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 LSB Field Branch Address Reset Unchanged Addr SPR 8 Figure 3-9. Link Register (LR) 3-20 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 137: Count Register (Ctr)
The VEA includes the time base register (TB), a 64-bit structure that contains a 64-bit unsigned integer that is incremented periodically. The frequency at which the counter is updated is implementation-dependent. For details on the time base clock in the MPC533, refer to Section 6.1.7, “Time Base (TB),” Section 8.5, “Internal Clock Signals,” and Section 8.11.1, “System Clock Control Register (SCCR).”...
Page 138: Oea Register Set
ID(21) Figure 3-12. Machine State Register (MSR) This bit is available only on code compression-enabled options of the MPC533. The reset value is a reset configuration word value extracted from the internal bus line. Refer toSection 7.5.2, “Hard Reset Configuration Word (RCW).”...
Page 139 Exception little-endian mode. When an exception occurs, this bit is copied into MSR[LE] to select the endian mode for the context established by the exception. Little-endian mode is not supported on the MPC533. This bit should be cleared to 0 at all times. 0 The processor runs in big-endian mode during exception processing.
Page 140: Dae/Source Instruction Service Register (Dsisr)
0 Machine state is not recoverable. 1 Machine state is recoverable. Little-endian mode. This mode is not supported on MPC533. This bit should be cleared to 0 at all times. 0 The processor operates in big-endian mode during normal processing.
Page 141: Data Address Register (Dar)
It is not possible to write the entire 64-bit time base in a single instruction. For information about reading the time base, refer to Section 3.8, “VEA Register Set — Time Base (TB).” MOTOROLA Chapter 3. Central Processing Unit 3-25...
Page 142: Decrementer Register (Dec)
The machine status save/restore register 0 (SRR0), SPR 26, identifies where instruction execution should resume when an rfi instruction is executed following an exception. It also holds the effective address of the instruction that follows the system call (sc) instruction. 3-26 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 143: Machine Status Save/Restore Register 1 (Srr1)
MSR[16:31] are placed into SRR1[16:31]. 3.9.8 General SPRs (SPRG0–SPRG3) SPRG0–SPRG3, SPRs 272-275, are provided for general operating system use, such as fast-state saves and multiprocessor-implementation support. SPRG0–SPRG3 are shown below. MOTOROLA Chapter 3. Central Processing Unit 3-27 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 144: Processor Version Register (Pvr)
Description 0:15 VERSION A 16-bit number that identifies the version of the processor and of the MPC500 architecture. The MPC533 value is 0x0002. 16:31 REVISION A 16-bit number that distinguishes between various releases of a particular version. The MPC533 value is 0x0020.
Page 145: Implementation-Specific Sprs
Field — DNC DNB DNA HRESET 0000_0000_0000_0000 Addr SPR 1022 Figure 3-21. Floating-Point Exception Cause Register (FPECR) A listing of FPECR bit settings is shown in Table 3-18. MOTOROLA Chapter 3. Central Processing Unit 3-29 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 146: Additional Implementation-Specific Registers
Software must insert a sync instruction before reading the FPECR. 3.9.10.3 Additional Implementation-Specific Registers Refer to the following sections for details on additional implementation-specific registers in the MPC533: • Section 4.6, “BBC Programming Model” • Section 6.2.2.1.2, “Internal Memory Map Register (IMMR)” • Section 11.8, “L2U Programming Model”...
Page 147 The MPC500 architecture uses instructions that are four bytes long and word-aligned. It provides for byte, half-word, and word operand loads and stores between memory and a set of 32 GPRs. MOTOROLA Chapter 3. Central Processing Unit 3-31...
Page 148: Instruction Set Summary
(bclrl) BO,BI Branch Conditional to Link Register crfD,L,rA,rB Compare cmpi crfD,L,rA,SIMM Compare Immediate cmpl crfD,L,rA,rB Compare Logical cmpli crfD,L,rA,UIMM Compare Logical Immediate cntlzw (cntlzw.) rA,rS Count Leading Zeros Word 3-32 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 149 Floating Multiply-Subtract Single fmul (fmul.) frD,frA,frC Floating Multiply (Double-Precision) fmuls (fmuls.) frD,frA,frC Floating Multiply Single fnabs (fnabs.) frD,frB Floating Negative Absolute Value fneg (fneg.) frD,frB Floating Negate MOTOROLA Chapter 3. Central Processing Unit 3-33 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 150 Load Hal-Word and Zero with Update Indexed lhzx rD,rA,rB Load Half-Word and Zero Indexed rD,d(rA) Load Multiple Word lswi rD,rA,NB Load String Word Immediate lswx rD,rA,rB Load String Word Indexed 3-34 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 151 (neg. nego nego.) rD,rA Negate nor (nor.) rA,rS,rB or (or.) rA,rS,rB (orc.) rA,rS,rB OR with Complement rA,rS,UIMM OR Immediate oris rA,rS,UIMM OR Immediate Shifted — Return from Interrupt MOTOROLA Chapter 3. Central Processing Unit 3-35 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 152 Store Multiple Word stswi rS,rA,NB Store String Word Immediate stswx rS,rA,rB Store String Word Indexed rS,d(rA) Store Word stwbrx rS,rA,rB Store Word Byte-Reverse Indexed stwcx. rS,rA,rB Store Word Conditional Indexed 3-36 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 153: Recommended Simplified Mnemonics
The MPC500 architecture supports two simple memory addressing modes: • EA = (rA|0) + 16-bit offset (including offset = 0) (register indirect with immediate index) • EA = (rA|0) + rB (register indirect with index) MOTOROLA Chapter 3. Central Processing Unit 3-37 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 154: Exception Model
Instruction execution continues until the next exception condition is encountered. This method of recognizing and handling exception conditions sequentially guarantees that the machine state is recoverable and processing can resume without losing instruction results. 3-38 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 155: Exception Classes
3.11.2 Ordered Exceptions In the MPC533, all exceptions except for reset, debug port non-maskable interrupts, and machine check exceptions are ordered. Ordered exceptions satisfy the following criteria: • Only one exception is reported at a time. If, for example, a single instruction encounters multiple exception conditions, those conditions are encountered sequentially.
Page 156: Precise Exceptions
“Exception Table Relocation (ETR).” 3.12 Instruction Timing The MPC533 processor is pipelined. Because the processing of an instruction is broken into a series of stages, an instruction does not require the entire resources of the processor. The instruction pipeline in the MPC533 has four stages: 1.
Page 157 Table 3-22 indicates the latency and blockage for each type of instruction. Latency refers to the interval from the time an instruction begins execution until it produces a result that is available for use by a subsequent instruction. Blockage refers to the interval from the MOTOROLA Chapter 3. Central Processing Unit 3-41...
Page 158: User Instruction Set Architecture (Uisa)
In most cases, the reserved fields in registers are ignored on write and return zeros for them on read on any control register implemented by the MPC533. Exception to this rule are bits 3-42 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 159: Classes Of Instructions
For performance of various instructions, refer to Table 3-22 of this manual. 3.13.7.1 Invalid Branch Instruction Forms Bits marked with z in the BO encoding definition are discarded by the MPC533 decoding. Thus, these types of invalid form instructions yield results of the defined instructions with the z-bit zero.
Page 160: Branch Prediction
In 32-bit implementations, if L = 1 the instruction form is invalid. The core ignores this bit and therefore, the behavior when L = 1 is identical to the valid form instruction with L = 0 3-44 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 161: Floating-Point Processor
3.13.9 Floating-Point Processor 3.13.9.1 General The MPC533 implements all floating-point features as defined in the UISA, including the non-IEEE working mode. Some features require software assistance. For more information refer to the RCPU Reference Manual (Floating-point Load Instructions) for more information.
Page 162: Floating-Point Load And Store With Update Instructions
3.14 Virtual Environment Architecture (VEA) 3.14.1 Atomic Update Primitives Both the lwarx and stwcx instructions are implemented according to the MPC500 architecture requirements. The MPC533 does not provide support for snooping an external 3-46 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 163: Effect Of Operand Placement On Performance
The effect of operand placement on performance is as stated in the VEA, except for the case of 8-byte operands. In that case, since the MPC533 uses a 32-bit wide data bus, the performance is good rather than optimal.
Page 164: Branch Processor Registers
The IP bit initial state after reset is set as programmed by the reset configuration as specified by the USIU characteristics. 3.15.1.2 Branch Processors Instructions The MPC533 implements all the instructions defined for the branch processor in the UISA in the hardware. 3.15.2 Fixed-Point Processor 3.15.2.1 Special Purpose Registers...
Page 165: System Reset Exception And Nmi (0X0100)
Bit is copied from ILE DCMPEN This bit is set according to (BBCMCR[EN_COMP] and BBCMCR[EXC_COMP]) Other Cleared to 0 If MPC5xx is in DecompressionOn mode, SRR0 will contain a compressed address. MOTOROLA Chapter 3. Central Processing Unit 3-49 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 166: Machine Check Exception (0X0200)
An indication is sent to the SIU which may generate an automatic reset in this condition. Refer to Chapter 7, “Reset,” for more details. The register settings for machine check exceptions are shown in Table 3-27. 3-50 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 167: Data Storage Exception (0X0300)
3.15.4.3 Data Storage Exception (0x0300) A data storage exception is never generated by the hardware. The software may branch to this location as a result of implementation-specific data storage protection error exception. MOTOROLA Chapter 3. Central Processing Unit 3-51 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 168: Instruction Storage Exception (0X0400)
(after retiring all instructions that are ready to retire). The enhanced interrupt controller mode is available for interrupt-driven applications on MPC533. It allows the single external interrupt exception vector 0x500 to be split into up to 48 different vectors corresponding to 48 interrupt sources to speed up interrupt processing.
Page 169: Alignment Exception (0X00600)
No change No change Set to value of ILE bit prior to the exception DCMPEN This bit is set according to (BBCMCR[EN_COMP] and BBCMCR[EXC_COMP]) Other Cleared to 0 MOTOROLA Chapter 3. Central Processing Unit 3-53 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 170 (If there is no corresponding instruction, no alternative value can be specified.) When an alignment exception is taken, instruction execution resumes at offset 0x00600 from the physical base address indicated by MSR[IP]. 3-54 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 171: Program Exception (0X0700)
This includes all illegal instructions and optional instructions not implemented in the RCPU. The register settings for program exceptions are shown in Table 3-30. MOTOROLA Chapter 3. Central Processing Unit 3-55 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 172: Floating-Point Unavailable Exception (0X0800)
A floating-point unavailable exception occurs when no higher priority exception exists, an attempt is made to execute a floating-point instruction (including floating-point load, store, and move instructions), and the floating-point available bit in the MSR is disabled, (MSR[FP] = 0). 3-56 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 173: Decrementer Exception (0X0900)
Setting Description Save/Restore Register 0 (SRR0) Set to the effective address of the instruction that the processor would have attempted to execute next if no exception conditions were present. MOTOROLA Chapter 3. Central Processing Unit 3-57 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 174: System Call Exception (0X0C00)
Register Setting Description Save/Restore Register 0 (SRR0) Set to the effective address of the instruction following the System Call instruction Save/Restore Register 1 (SRR1) [0:15] Undefined [16:31] Loaded from MSR[16:31] 3-58 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 175: Trace Exception (0X0D00)
If the exception occurs during an instruction fetch in Decompression On mode, the SRR0 register will contain a compressed address. Execution resumes at offset 0x0D00 from the base address indicated by MSR[IP]. MOTOROLA Chapter 3. Central Processing Unit 3-59 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 176: Floating-Point Assist Exception (0X0E00)
When a floating-point exception is taken, instruction execution resumes at offset 0x0E00 from the base address indicated by MSR[IP]. 3.15.4.13 Implementation-Dependent Software Emulation Exception (0x1000) An implementation-dependent software emulation exception occurs in the following instances: 3-60 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 177: Implementation-Dependent Instruction Protection Exception (0X1300)
• The fetch access violates storage protection and MSR[IR] = 1. • The fetch access is to guarded storage and MSR[IR] = 1. The register settings for instruction protection exceptions are shown in Table 3-37. MOTOROLA Chapter 3. Central Processing Unit 3-61...
Page 178: Implementation-Specific Data Protection Error Exception (0X1400)
Table 3-38. Register Settings Following a Data Protection Error Exception Register Name Bits Description Save/Restore Register 0 (SRR0) Set to the effective address of the instruction that caused the exception 3-62 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 179: Implementation-Dependent Debug Exceptions
“Development Support.” • When a peripheral breakpoint request is asserted to the MPC533 core. • When the development port request is asserted to the MPC533 core. Refer to Chapter 21, “Development Support,” for details on how to generate the development port-interrupt request.
Page 180: Partially Executed Instructions
In general, the architecture permits instructions to be partially executed when an alignment or data storage interrupt occurs. In the core, instructions are not executed at all if an alignment interrupt condition is detected and data storage interrupt is never generated by 3-64 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 181: Timer Facilities
Operating Environment Architecture (OEA) the hardware. In the MPC533, the instruction can be partially executed only in the case of the load/store instructions that cause multiple accesses to the memory subsystem. These instructions are: • Multiple/string instructions • Unaligned load/store instructions In the last case, the store instruction can be partially completed if one of the accesses (except the first one) causes the data storage protection error.
Page 182 Operating Environment Architecture (OEA) 3-66 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 183: Burst Buffer Controller 2 Module
The IMPU is able to relocate the RCPU exception vectors. The IMPU always maps the exception vectors into the internal memory space of the MPC533. This feature is important for a multi-MPC533 system, where, although the internal memories of some controllers are not shifted to the lower 4 Mbytes, they can still have their own internal exception vector tables with the same exception addresses issued by their RCPU cores.
Page 184: Key Features
— An access violation of protection attributes — A fetch from a guarded region. • The RCPU MSR[IR] bit controls IMPU protection. • Programming is performed by using the RCPU mtspr/mfspr instructions to/from implementation specific special-purpose registers. MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 185: Icdu Key Features
Branch Target Buffer Key Features • Consists of eight “branch target entries” (BTE). Each entry contains: — A 32-bit register that stores the target of historical change of flow (COF) address MOTOROLA Chapter 4. Burst Buffer Controller 2 Module PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 186: Operation Modes
Show cycle, program trace and debug port access attributes accompanying the RCPU access are forwarded by the BIU along with the U-bus access. 4.2.1.2 Decompression On Mode See Appendix G, “MPC534 Compression Features” for explanation of the decompression on mode. MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 187: Burst Operation And Access Violation Detection
4.2.5 Debug Operation Mode When the MPC533 RCPU core is in debug mode, the BBC initiates non-burstable access to the debug port and ICDU is bypassed (i.e., instructions transmitted to the debug port must be non-compressed regardless of operational mode).
Page 188: Exception Table Relocation (Etr)
The exception vector table may be programmed to be located in four places in the MPC533 internal memory space. The exception table relocation is supported in both decompression on and decompression off operation modes.
Page 189: Etr Operation
If the exception table relocation is disabled by the ETRE bit in the BBCMCR register, the BBC transfers the exception fetch address to the U-bus of the MPC533 with no interference. In this case, normal PowerPC exception addressing is implemented.
Page 190 The 8 Kbytes allocated for the original PowerPC exception table can be almost fully utilized. This is possible if the MPC533 system memory is NOT mapped to the exception address space, (i.e., the addresses 0xFFF0_0000 to 0xFFF0_1FFF are not used).
Page 191: Enhanced External Interrupt Relocation (Eeir)
4.3.3 Enhanced External Interrupt Relocation (EEIR) The BBC also supports the enhanced external interrupt model of the MPC533 which allows the removal of the interrupt requesting a source detection stage from the interrupt routine. The interrupt controller provides the interrupt vector to the BBC together with an interrupt request to the RCPU.
Page 192 EEIR mechanism. When the EEIR function is activated, any branch instruction execution with the 0xFFF0_0500 target address may cause unpredictable program execution. 4-10 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 193: Decompressor Ram (Decram) Functionality
In the case of decompression off mode, the DECRAM can serve as a two-clock access general-purpose RAM for U-bus instruction fetches or four-clock access for read/write data operations. The base address of the DECRAM is 0x2F 8000. See Figure 4-6. The proper MOTOROLA Chapter 4. Burst Buffer Controller 2 Module 4-11...
Page 194: Memory Protection Violations
The DECRAM module does not acknowledge U-bus accesses that violate the configuration defined in the BBCMCR. This causes the machine check exception for the internal RCPU or an error condition for the MPC533 external master. 4.4.1.2 DECRAM Standby Operation Mode The bus interface and DECRAM control logic are powered by V supply.
Page 195: Btb Operation
RCPU after all the stored instructions in the matched BTB entry were delivered. In case of a BTB hit, the impact of instruction decompression latency is eliminated as well as a latency of instruction storage memory device. MOTOROLA Chapter 4. Burst Buffer Controller 2 Module 4-13 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 196: Btb Invalidation
The BTB operation may be inhibited regarding some memory regions. The BTB caching is inhibited for a region if the BTBINH bit is set in the region attribute register (or global 4-14 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 197: Bbc Programming Model
RCPU mtspr/mfspr instructions. 2. Decompressor vocabulary RAM (DECRAM). The DECRAM array occupies the 4-Kbyte physical memory (8 Kbytes MPC533 address space is allocated for DECRAM). 3. Decompressor class configuration registers (DCCR) block. It consists of 15 decompression class configuration registers.
Page 198 Figure 4-7. BBC Module Configuration Register (BBCMCR) MPC534 only. The reset value is a reset configuration word value extracted from the internal bus line. Refer toSection 7.5.2, “Hard Reset Configuration Word (RCW).” 4-16 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 199 0 “Decompression ON” mode is disabled. The MPC534 operates only in “Decompression OFF” mode. 1 “Decompression ON” mode is enabled. The MPC534 may operate with both “Decompression ON” and “Decompression OFF” modes. MOTOROLA Chapter 4. Burst Buffer Controller 2 Module 4-17 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 200 The reset value is determined by reset configuration word bit #22. 0 The MPC533 assumes that exception routines are noncompressed 1 The MPC534 assumes that all exception routines are compressed.
Page 201 Field — CMPR BTBINH — HRESET Undefined Undefined Addr SPR 816 (MI_RA0), SPR 817 (MI_RA1), SPR 818 (MI_RA2), 819 (MI_RA3) Figure 4-9. Region Attribute Register (MI_RA0[0:3]) MOTOROLA Chapter 4. Burst Buffer Controller 2 Module 4-19 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 202 0000_0000_0000_0000_1111 64 Kbytes 0000_0000_0000_0001_1111 128 Kbytes 0000_0000_0000_0011_1111 256 Kbytes 0000_0000_0000_0111_1111 512 Kbytes 0000_0000_0000_1111_1111 1 Mbyte 0000_0000_0001_1111_1111 2 Mbytes 0000_0000_0011_1111_1111 4 Mbytes 0000_0000_0111_1111_1111 8 Mbytes 0000_0000_1111_1111_1111 16 Mbytes 0000_0001_1111_1111_1111 32 Mbytes 4-20 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 203 Enable IMPU Region 2 0 Region 2 is off. 1 Region 2 is on. ENR3 Enable IMPU Region 3 0 Region 3 is off. 1 Region 3 is on. MOTOROLA Chapter 4. Burst Buffer Controller 2 Module 4-21 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 204 4.6.2.5 External Interrupt Relocation Table Base Address Register (EIBADR) Field HRESET Undefined Field — HRESET Undefined 0000_0000_0000 Addr SPR 529 Figure 4-11. External Interrupt Relocation Table Base Address Register (EIBADR) 4-22 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 205 Reserved. EIBADR must be set on a 4K page boundary. 4.6.3 Decompressor Class Configuration Registers See Section G.4, “Decompressor Class Configuration Registers (DCCR0-15)” for the registers of the ICDU. MOTOROLA Chapter 4. Burst Buffer Controller 2 Module 4-23 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 206 BBC Programming Model 4-24 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 207 I/O, external 32-bit port that supports internal and external masters, and various debug functions. Reset logic for the MPC533 provides soft and hard resets, checkstop and watchdog resets, and other types of reset. The reset status register (RSR) reflects the most recent source to cause a reset.
Page 208 Refer to Chapter 19, “CDR3 Flash (UC3F) EEPROM.” It is not possible to operate the MPC533 from the external world while the flash is in censorship mode and in a censorship state. The internal flash array will be either locked or accessible only after the entire array contents have been erased.
Page 209 32 bits wide. The address shown for each register is relative to the base address of the MPC533 internal memory map. The internal memory block can reside in one of eight possible 4 Mbyte memory spaces. See Figure 1-3 for details.
Page 210 Base Register 0 (BR0) See Table 10-9 for bit descriptions. 0x2F C104 Option Register 0 (OR0) See Table 10-11 for bit descriptions. 0x2F C108 Base Register 1 (BR1) See Table 10-9 for bit descriptions. MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 211 See Section 6.2.2.4.7, “Real-Time Clock Alarm Register (RTCAL),” for bit descriptions. 0x2F C230–0x2F C23C Reserved 0x2F C240 PIT Status and Control (PISCR) See Table 6-20 for bit descriptions. MOTOROLA Chapter 5. Unified System Interface Unit (USIU) Overview PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 212 See Table 8-8 for bit descriptions. 0x2F C32C Real-Time Alarm Key (RTCALK) See Table 8-8 for bit descriptions. 0x2F C330–0x2F C33C Reserved 0x2F C340 PIT Status and Control Key (PISCRIK) See Table 8-8 for bit descriptions. MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 213 5.1.1 USIU Special-Purpose Registers Table 5-2 lists the MPC533 special purpose registers (SPR) used by the USIU. These registers reside in an alternate internal memory space that can only be accessed with the mtspr and mfspr instructions, or from an external master (refer to Section 6.1.2, “External Master Modes,”...
Page 214 See Table 6-12 for bit descriptions. Bits [0:17] and [28:31] are all 0. Table 5-3 shows the MPC533 address format for special purpose register access. For an external master, accessing an MPC500 SPR, address bits [0:17] and [28:31] are compared to zeros to confirm that an SPR access is valid.
Page 215 This binary counter is clocked by the same frequency as the time base (also defined by the MPC533 architecture). The period for the DEC when driven by a 4-MHz oscillator can be up to 4295 seconds, which is approximately 71.6 minutes.
Page 216 • Low Power Stop (Section 6.1.12, “Low Power Stop Operation”)—In low power modes, specific timers are frozen but others are not. Figure 6-1 shows a block diagram of the system configuration and protection logic. MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 217 The functions include control of show cycle operation, pin multiplexing, and internal memory map location. System configuration also includes a register containing part and mask number constants to identify the part in software. MOTOROLA Chapter 6. System Configuration and Protection PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 218 (internal arbitration), the external arbitration request priority (EARP) bit determines the priority of an external master’s arbitration request. The operation of the internal arbiter is described in Section 9.5.7.4, “nternal Bus Arbiter.” MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 219 The MPC533 does not support burst accesses from an external master; only single accesses of 8, 16, or 32 bits can be performed. The MPC533 asserts burst inhibit (BI) on any attempt to initiate a burst access to internal memory.
Page 220 Refer to Section 6.2.2.1.3, “External Master Control Register (EMCR)”. • MPC533 special register external access. If the CONT bit in EMCR is set by the previous external master access, the address is compared to the MPC533 special address range.
Page 221 SDDRD[23:31] SGPIOC[0:7] SDDRC[0:7] SGPIOA[8:15] GDDR3 SGPIOA[16:23] GDDR4 SGPIOA[24:31] GDDR5 SGPIOC[0:7] is selected according to GPC and MLRC fields in SIUMCR. See Section 6.2.2.1.1, “SIU Module Configuration Register (SIUMCR).” MOTOROLA Chapter 6. System Configuration and Protection PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 222 • Full backward compatibility with MPC555/MPC556 (enhanced mode is software programmable.) 6.1.4.2 Interrupt Configuration An overview of the MPC533 interrupt structure is shown in Figure 6-5. The interrupt controller receives interrupts from USIU internal sources, such as PIT, RTC, from the MPC533 Reference Manual MOTOROLA...
Page 223 Levels[0:7] IMBIRQ Sequencer ilbs[0:1] USIU Figure 6-3. MPC533 Interrupt Structure If programmed to generate an interrupt, the SWT and external pin IRQ[0] always generate an NMI, non-maskable interrupt to the RCPU. MOTOROLA Chapter 6. System Configuration and Protection PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 224 The SIVEC register contains an 8-bit code representing the unmasked interrupt request which has the highest priority level. The priority between all interrupt sources for the regular interrupt controller operation is shown in Table 6-3. 6-10 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 225 The priority logic is provided in order to determine the highest unmasked interrupt request, and interrupt code is generated in the SIVEC register. See Table 6-4. MOTOROLA Chapter 6. System Configuration and Protection 6-11 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 226 01101000 — IMB_IRQ 17 0x00D8 01101100 — IMB_IRQ 18 0x00E0 01110000 — IMB_IRQ 19 0x00E8 01110100 — EXT_IRQ5 0x00F0 01111000 — Level 5 0x00F8 01111100 — IMB_IRQ 20 0x0100 10000000 6-12 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 227 Lower Priority Request Masking This feature (if enabled) simplifies the masking of lower priority interrupt requests when a request of certain priority is in service in applications that require interrupt nesting. The MOTOROLA Chapter 6. System Configuration and Protection 6-13...
Page 228 EICEN control bit in SIUMCR register, which can be set and cleared at any time by software. If the bit is cleared, the default interrupt controller operation is 6-14 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 229 Section 6.1.4.3, “Regular Interrupt Controller Operation (MPC555/MPC556 Compatible Mode)”. The regular operation is fully compatible with the interrupt controller already implemented in MPC555/MPC556. Figure 6-7 illustrates the interrupt controller functionality in the MPC533. MOTOROLA Chapter 6. System Configuration and Protection 6-15 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 230 Encoder (6 from 48) (Enables branch to the highest priority interrupt routine) Enhanced Interrupt Controller Enabled Interrupt Request (to RCPU and IRQOUT pad) Figure 6-5. MPC533 Interrupt Controller Block Diagram 6-16 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 231 Recognition of module internal events/channels is out of the scope of the calculations. See also the typical interrupt handler flowchart in Figure 6-6. Table 6-5. Interrupt Latency Estimation for Three Typical Cases MPC533 Architecture Using MPC533 Architecture MPC533 Architecture Using...
Page 232 The USIU provides a bus monitor option to monitor internal to external bus accesses on the external bus. The monitor counts from transfer start to transfer acknowledge and from transfer acknowledge to transfer acknowledge within bursts. If the monitor times out, 6-18 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 233 This binary counter is clocked by the same frequency as the time base (also defined by the MPC533 architecture). The operation of the time base and decrementer are therefore coherent. The DEC is clocked by the TMBCLK clock.
Page 234 TB are restricted to special instructions. Separate special-purpose registers are defined in the MPC533 architecture for reading and writing the TB. For the MPC533 implementation, it is not possible to read or write the entire TB in a single instruction.
Page 235 When a new value is written into the PITC, the periodic timer is updated, the divider is reset, and the counter begins counting. If the PS bit is not cleared, an interrupt request is MOTOROLA Chapter 6. System Configuration and Protection 6-21 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 236 SYPCR register. The SWT can be disabled by clearing the SWE bit in the SYPCR. Once the SYPCR is written by software, the state of the SWE bit cannot be changed. 6-22 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 237 SWTC, the software watchdog timer is not updated until the servicing sequence is written to the SWSR. If the SWE is loaded with the value zero, the modulus counter does not count (i.e. SWTC is disabled). MOTOROLA Chapter 6. System Configuration and Protection 6-23...
Page 238 They continue to run at their respective frequencies. These timers are capable of generating an interrupt to bring the MCU out of these low-power modes. Memory Map and Register Definitions This section provides the MPC533 memory map, and diagrams and bit descriptions of the system configuration and protection registers. 6-24...
Page 239 6.2.1 Memory Map The MPC533 internal memory space can be assigned to one of eight locations. The internal memory map is organized as a single 4-Mbyte block. The user can assign this block to one of eight locations by programming the ISB field in the internal memory mapping register (IMMR).
Page 240 0 Disable show cycles for all internal data cycles 1 Show address and data of all internal data cycles 9:10 DBGC Debug pins configuration. Refer to Table 6-8. DBPC Reserved. 6-26 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 241 Refer to 10.2.5 Burst Support for more information. 29:31 — Reserved WE/BE is selected per memory region by WEBS in the appropriate BR register in the memory controller. MOTOROLA Chapter 6. System Configuration and Protection 6-27 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 242 00 (multiple chip, 32-bit port size) DATA[0:15] DATA[16:31] ADDR[8:31] 01 (multiple chip, 16-bit port size DATA[0:15] SPGIOD[16:31] ADDR[8:31] 10 (single-chip with address show SPGIOD[0:15] SPGIOD[16:31] ADDR[8:31] cycles for debugging) 11 (single-chip) SPGIOD[0:15] SPGIOD[16:31] SPGIOA[8:31] 6-28 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 243 6.2.2.1.2 Internal Memory Map Register (IMMR) The internal memory map register (IMMR) is a register located within the MPC533 special register space. The IMMR contains identification of a specific device as well as the base for the internal memory map. Based on the value read from this register, software can deduce availability and location of any on-chip system resources.
Page 244 111 0x01C0 0000 — Reserved 6.2.2.1.3 External Master Control Register (EMCR) The external master control register selects the external master modes and determines the internal bus attributes for external-to-internal accesses. 6-30 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 245 1 Operand or non-CPU access 23:24 — Reserved RESV Reservation attribute. RESV controls the internal bus reservation attribute as follows: 0 Storage reservation cycle 1 Not a reservation MOTOROLA Chapter 6. System Configuration and Protection 6-31 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 246 Bits Name Description CONT Control attribute. CONT drives the internal bus control bit attribute as follows: 0 Access to MPC533 control register, or control cycle access 1 Access to global address map — Reserved TRAC Trace attribute. TRAC controls the internal bus program trace attribute as follows:...
Page 247 IRQ4 LVL4 IRQ5 LVL5 IRQ10 IRQ11 IRQ12 IRQ13 IRQ14 IRQ15 IRQ16 IRQ17 IRQ18 IRQ19 SRESET 0000_0000_0000_0000 Addr 0x2F C040 Figure 6-16. SIU Interrupt Pending Register 2 (SIPEND2) MOTOROLA Chapter 6. System Configuration and Protection 6-33 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 248 NOTE To mask interrupt sources, first set the core’s status register interrupt mask level to that of the source being masked in SIMASK. Then, the SIMASK bit can be masked. 6-34 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 249 IRQ0 of the SIPEND2 register is not affected by the setting or clearing of the IRQ0 bit of the SIMASK2 register. IRQ0 is a non-maskable interrupt Figure 6-19. SIU Interrupt Mask Register 2 (SIMASK2) MOTOROLA Chapter 6. System Configuration and Protection 6-35...
Page 250 When the EDx bit is 0, a low logical level in the IRQ line will be detected as an interrupt request. The WMx (wake-up mask) bit, if set, indicates that an interrupt request detection in the corresponding line causes the MPC533 to exit low-power mode.
Page 251 BASE +1000 • BASE +10 • • • BASE + n • BASE + n • • Figure 6-23. Example of SIVEC Register Usage for Interrupt Table Handling MOTOROLA Chapter 6. System Configuration and Protection 6-37 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 252 Field IMB IRQ20 IRQ21 IRQ22 IRQ23 IRQ24 IRQ25 IRQ26 IRQ27 IRQ28 IRQ29 IRQ30 IRQ31 SRESET 0000_0000_0000_0000 Field — SRESET 0000_0000_0000_0000 Addr 0x2F C054 Figure 6-25. Interrupt In-Service Register 3 (SISR3) 6-38 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 253 0 Software watchdog time-out causes a non-maskable interrupt to the RCPU 1 Software watchdog time-out causes a system reset Software watchdog prescale 0 Software watchdog timer is not prescaled 1 Software watchdog timer is prescaled by 2048 MOTOROLA Chapter 6. System Configuration and Protection 6-39 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 254 Field — Reset 0000_0000_0000_0000 Field — IEXT IBMT — DEXT DBM — Reset 0000_0000_0000_0000 Addr 0x2F C020 Figure 6-28. Transfer Error Status Register (TESR) 6-40 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 255 Decrementer counts down the time base clock and the counting is enabled by TBE bit in TBCSR register Section 6.2.2.4.4, “Time Base Control and Status Register (TBSCR).” MOTOROLA Chapter 6. System Configuration and Protection 6-41 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 256 Two reference registers (TBREF0 and TBREF1) are associated with the lower part of the time base (TBL). Each is a 32-bit read/write register. Upon a match between the contents of TBL and the reference register, a maskable interrupt is generated. 6-42 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 257 REFA bit is set. REFBE Reference B (TBREF1) interrupt enable. If this bit is set, the time base generates an interrupt when the REFB bit is set. MOTOROLA Chapter 6. System Configuration and Protection 6-43 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 258 Alarm interrupt enable. If this bit is set, the RTC generates an interrupt when the ALR bit is set. Real-time clock freeze. If this bit is set, the RTC stops while FREEZE is asserted. Real-time clock enable 0 RTC is disabled 1 RTC is enabled 6-44 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 259 The PISCR contains the interrupt request level and the interrupt status bit. It also contains the controls for the 16-bits to be loaded into a modulus counter. This register can be read or written at any time. MOTOROLA Chapter 6. System Configuration and Protection 6-45...
Page 260 The PITC register contains the 16-bits to be loaded in a modulus counter. This register is readable and writable at any time. Field PITC Reset Unaffected Field — Reset Unaffected Addr 0x2F C244 Figure 6-39. Periodic Interrupt Timer Count (PITC) 6-46 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 261 General-Purpose I/O Registers 6.2.2.5.1 SGPIO Data Register 1 (SGPIODT1) Field SGPIOD[0:7] SGPIOD[8:15] Reset 0000_0000_0000_0000 Field SGPIOD[16:23] SGPIOD[24:31] Reset 0000_0000_0000_0000 Addr 0x2F C024 Figure 6-41. SGPIO Data Register 1 (SGPIODT1) MOTOROLA Chapter 6. System Configuration and Protection 6-47 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 262 SIU general-purpose I/O Group A[24:31]. This 8-bit register controls the data of the [24:31] general-purpose I/O pins SGPIOA[24:31]. The GDDR5 bit in the SGPIO control register configures these pins as a group as general-purpose input or output. 6-48 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 263 SGPIOD pin [24:31]. Table 6-26 describes the bit values for data direction control. Table 6-26. Data Direction Control SDDR/GDDR Operation SGPIO configured as input SGPIO configured as output MOTOROLA Chapter 6. System Configuration and Protection 6-49 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 264 Memory Map and Register Definitions 6-50 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 265 Reset This section describes the MPC533 reset sources, operation, control, and status. Reset Operation The MPC533 has several inputs to the reset logic which include the following: • Power-on reset • External hard reset pin (HRESET) • External soft reset pin (SRESET) •...
Page 266 • The Internal PLL enters the lock state and the system clock is active. • The PORESET pin is negated. If the MPC533 is in single-chip mode and limp mode is enabled, the internal PLL is not required to be locked before the chip exits power-on reset.
Page 267 DSCK pins and the chip stops driving the SRESET pin. An external pull-up resistor should drive the SRESET pin high. After the MPC533 detects the negation of SRESET, it waits 16 clock cycles before testing the presence of an external soft reset.
Page 268 • On-Chip Clock Switch • Illegal Low-Power Mode • Software Watchdog • Checkstop • Debug Port Hard Reset Soft Reset (SRESET) Sources: • External Soft Reset • Debug Port Soft Reset • JTAG Reset MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 269 SRESET/HRESET is asserted and the external reset configuration word (RCW) is used. In this case, the external RCW drivers, usually activated by HRESET/SRESET lines, will drive the RCW together with the MPC533. Thus the data in the RAM may be corrupted regardless of data coherency mechanism in the MPC533.
Page 270 0 No on-chip clock switch reset has occurred 1 An on-chip clock switch reset has occurred ILBC Illegal bit change. This bit is set when the MPC533 changes any of the following bits when they are locked: LPM[0:1], locked by the LPML bit...
Page 271 7.5.1 Hard Reset Configuration When a hard reset event occurs, the MPC533 reconfigures its hardware system as well as the development port configuration. The logical value of the bits that determine its initial mode of operation, are sampled from the following: •...
Page 272 If the PRDS control bit in the PDMCR register is set and HRESET and RSTCONF are asserted, the MPC533 pulls the data bus low with a weak resistor. The user can overwrite this default by driving the appropriate bit high. See Figure 7-2 for the basic reset configuration scheme.
Page 273 Timing diagrams in the following figures are not to scale. CLKOUT PORESET Internal poreset HRESET RSTCONF Tsup Internal data[0:31] Default RSTCONF Controlled Figure 7-3. Reset Configuration Sampling Scheme For “Short” PORESET Assertion, Limp Mode Disabled MOTOROLA Chapter 7. Reset PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 274 “Short” PORESET Assertion, Limp Mode Enabled CLKOUT PORESET PLL lock Internal poreset HRESET Tsup RSTCONF Internal data[0:31] Default RSTCONF Controlled Figure 7-5. Reset Configuration Timing for “Long” PORESET Assertion, Limp Mode Disabled 7-10 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 275 — DBGC[0:1] — ATWC EBDF[0:1] — HRESET 0000_0000_0000_0000 Field PRPM ETRE FLEN EXC_ — OERC — COMP COMP HRESET 0000_0000_0000_0000 Figure 7-7. Reset Configuration Word (RCW) Available only on the MOTOROLA Chapter 7. Reset 7-11 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 276 PRPM Peripheral Mode Enable — This bit determines if the chip is in peripheral mode. A detailed description is in Table 6-13 The default value is no peripheral mode enabled. 7-12 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 277 0 Dual mapping disabled 1 Dual mapping enabled Available only on the MPC534 7.5.3 Soft Reset Configuration When a soft reset event occurs, the MPC533 reconfigures the development port. Refer to Chapter 21, “Development Support,” for details. MOTOROLA Chapter 7. Reset 7-13...
Page 278 Reset Configuration 7-14 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 279 KAPWR is powered to the same voltage value as the voltage of the I/O buffers and logic. The MPC533 clock module consists of the main crystal oscillator, the SPLL, the low-power divider, the clock generator, the system low-power control block, and the limp mode control block.
Page 280 Drivers ENGCLK TMBCLK TMBCLK Driver Back_Up Clock Oscillator Loss Detector RTC / PIT Clock PITRTCLK and Driver /4 or /256 XTAL Main Clock Oscillator EXTAL Figure 8-1. Clock Unit Block Diagram MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 281 PLL, the skew between the EXTCLK pin and the CLKOUT is less than 1 ns. The backup clock on-chip ring oscillator allows the MPC533 to function with a less precise clock. When operating from the backup clock, the MPC533 is in limp mode. This enables the system to continue minimum functionality until the system is fixed.
Page 282 GCLK1 and GCLK2 clocks. On power-up, with a 4-MHz or 20-MHz crystal and the default MF settings, VCOOUT will be 40 MHz and the system clock will be 20 MHz. MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 283 (DFNH) and division factor low frequency (DFNL) bits in SCCR are set to the value of 0 (÷1 for DFNH and ÷2 for DFNL). MOTOROLA Chapter 8. Clocks and Power Control PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 284 LOLRE (loss of lock reset enable) bit in the PLPRCR is cleared, the system clock source continues to function as the PLL’s output clock. The USIU timers can operate with the input MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 285 This block generates all other clocks in normal operation, but has the ability to divide the output frequency of the VCO before it generates the general system clocks sent to the rest of the MPC533. The PLL VCOOUT is always divided by at least two.
Page 286 When DFNH = 0, GCLK2_50 has a 50% duty cycle. With other values of DFNH or DFNL, the duty cycle is less than 50%. Refer to Figure 8-7. GCLK1_50 rises simultaneously with GCLK1. When the MPC533 is not in gear mode, the falling edge of GCLK1_50 occurs in MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 287 IRQ[5:7] are used as interrupts, the interrupt source should be removed during PORESET to insure the MODCK pins are in the correct state on the rising edge of PORESET. MOTOROLA Chapter 8. Clocks and Power Control PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 288 The RTDIV bit value in the SCCR register defines the division of PITRTCLK. All possible combinations of the TMBCLK divisions are listed in Table 8-2. Table 8-2. TMBCLK Divisions TMBCLK SCCR[TBS] MF + 1 Division — 1, 2 > 2 8-10 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 289 General System Clocks The general system clocks (GCLK1C, GCLK2C, GCLK1, GCLK2, GCLK1_50, and GCLK2_50) are the basic clock supplied to all modules and sub-modules on the MPC533. GCLK1C and GCLK2C are supplied to the RCPU and to the BBC. GCLK1C and GCLK2C are stopped when the chip enters the doze-low power mode.
Page 290 FREQsysmax = VCOOUT/2 Therefore, the complete equation for determining the system clock frequency is: (MF + 1) OSCCLK System Frequency= DIVF + 1 (2 DNFH ) or (2 DFNL + 1) 8-12 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 291 CQDS bits. (See Section 8.11.1, “System Clock Control Register (SCCR)”). Disabling or decreasing the strength of CLKOUT can reduce power consumption, noise, and electromagnetic interference on the printed circuit board. MOTOROLA Chapter 8. Clocks and Power Control 8-13 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 292 BUCLK. After HRESET negation the PLL lock condition does not effect the system clock source selection. 8-14 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 293 4, osc buclk_enable = 0 & hreset_b = 0 buclk_enable = 1 else & hreset_b = 0 5, osc 6,BULCK Figure 8-8. Clock Source Switching Flow Chart MOTOROLA Chapter 8. Clocks and Power Control 8-15 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 294 DFNL bits. The normal-high operating mode is the state out of reset. This is also the state of the bits after the low-power mode exit signal arrives. There are four low-power modes: • Doze mode • Sleep mode 8-16 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 295 Powered-Up Normal-high Active Full frequency ÷ Full functions not in use All On DFNH are shut off Normal-low (“gear”) Active Full frequency ÷ All On DFNL+1 MOTOROLA Chapter 8. Clocks and Power Control 8-17 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 296 TMIST is set. The TMIST status bit should be cleared before entering any low-power mode. Table 8-7 summarizes wake-up operation for each of the low-power modes. 8-18 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 297 In deep-sleep mode the PLL is disabled. The wake-up time from this mode is up to 500 PLL input frequency clocks. In one-to-one mode the wake-up time may be up to 100 PLL input MOTOROLA Chapter 8. Clocks and Power Control 8-19 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 298 Refer to Section 8.8.3, “Keep-Alive Power” for more information. 8.7.3.5 Low-Power Modes Flow Figure 8-9 shows the flow among the different power modes. 8-20 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 299 TEXPS receives the zero value by writing one. Writing of zero has no effect on TEXPS. The switch from normal-high to normal-low is enable only if the conditions to asynchronous interrupt are cleared. Figure 8-9. MPC533 Low-Power Modes Flow Diagram MOTOROLA Chapter 8.
Page 300 PPC RTC, PIT, TB, and DEC 8.8.2 Chip Power Structure The MPC533 provides a wide range of possibilities for power supply connections. Figure 8-10 illustrates the different power supply sources for each of the basic units on the chip. 8.8.2.1 NVDDL This supplies the final output stage of the 2.6-V pad output drivers.
Page 301 Basic Power Structure 8.8.2.3 VDD powers the internal logic of the MPC533, nominally 2.6V. 8.8.2.4 VDDSYN, VSSSYN The charge pump and the VCO of the SPLL are fed by a separate 2.6-V power supply (VDDSYN) in order to improve noise immunity and achieve a high stability in its output frequency.
Page 302 Supply Figure 8-11. External Power Supply Scheme The MPC533 asserts the TEXP signal, if enabled, when the RTC or TB time value matches the value programmed in the associated alarm register or when the PIT or DEC value reaches zero. The TEXP signal is negated when the TEXPS status bit is written to one.
Page 303 To minimize the possibility of data loss, the MPC533 includes a key mechanism that ensures data retention as long as a register is locked. While a register is locked, writes to this register are ignored.
Page 304 LVSR bits are read as one, then a power failure of has occurred. The circuit is capable of detecting supply failure below a voltage level to be determined. Also, 8-26 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 305 If the turn-off voltage of the power supply chip is greater than 0.74 V for the 2.6-V supply and greater than 0.8 V for the 5-V supply, then the circuitry inside the MPC533 will act as a load to the respective supply and will discharge the supply line down to these values.
Page 306 Power-Up/Down Sequencing NOTE Power Off Operating Power On See Note 1. See Note 2. VDDH VDD, NVVL, QVDDL KAPWR IRAMSTBY VDDA, VRH VDDSYN VFLASH (5 V) PORESET HRESET 8-28 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 307 Section K.8, “Power-Up/Down Sequencing.” 8.11 Clocks Unit Programming Model 8.11.1 System Clock Control Register (SCCR) The SPLL has a 32-bit control register, SCCR, which is powered by keep-alive power. MOTOROLA Chapter 8. Clocks and Power Control 8-29 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 308 The default value for COM[1] is determined by the BDRV bit in the reset configuration word. See Table 7-5. For CLKOUT control see Table 8-10. 8-30 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 309 1 Switches to high frequency (defined by DFNH) when the power management bit in the MSR is reset (normal operational mode) or there is a pending interrupt from the interrupt controller MOTOROLA Chapter 8. Clocks and Power Control 8-31 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 310 NOTE: If the engineering clock division factor is not a power of two, synchronization between the system and ENGCLK is not guaranteed. — Reserved 8-32 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 311 Clock Output Disabled, Bus pins reduced drive 8.11.2 PLL, Low-Power, and Reset-Control Register (PLPRCR) The PLL, low-power, and reset-control register (PLPRCR) is a 32-bit register powered by the keep-alive power supply. MOTOROLA Chapter 8. Clocks and Power Control 8-33 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 312 0 No loss of oscillator has been detected 1 Loss of oscillator has been detected SPLS System PLL lock status bit 0 SPLL is currently not locked 1 SPLL is currently locked 8-34 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 313 This bit is writable once after soft reset. 0 No reset will occur when checkstop is asserted 1 Reset will occur when checkstop is asserted MOTOROLA Chapter 8. Clocks and Power Control 8-35 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 314 This register is readable and writable at any time. A status bit is cleared by writing a one (writing a zero does not affect a status bit’s value). The COLIR is mapped into the MPC533 USIU register map. Field...
Page 315 NOTE: The LVDRS bit is provided as a convenience for indicating that the DECRAM has lost power. It requires that the 3 pins are connected to the same power supply. It actually only monitors the supply. — Reserved MOTOROLA Chapter 8. Clocks and Power Control 8-37 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 316 Clocks Unit Programming Model 8-38 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 317 • Easy to interface to slave devices • Bus is synchronous (all signals are referenced to rising edge of bus clock) • Bus can operate at the same frequency as the internal RCPU core of MPC533 or half the frequency.
Page 318 For all inputs, the MPC533 latches the level of the input during a sample window around the rising edge of the clock signal. This window is illustrated in Figure 9-1, where t are the input setup and hold times, respectively.
Page 319 ADDR[8:31] RD/WR BURST TSIZ[0:1] Address AT[0:3] Transfer Attributes BDIP Transfer Start Interface Reservation Protocol DATA[0:31] Data BI / STS Transfer Cycle Termination Arbitration RETRY Figure 9-2. MPC533 Bus Signals MOTOROLA Chapter 9. External Bus Interface PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 320 Address bus [8:31] external bus. An input for testing purposes only. Driven by the MPC533 along with the address when it owns the external bus. Driven high indicates that a RD/WR read access is in progress. Driven low indicates that a HIgh write access is in progress.
Page 321 Table 9-1. MPC533 SIU Signals (continued) Signal Name Pins Active Description Driven by the MPC533 along with the address when it High owns the external bus. Indicates additional information about the address on the current transaction. Program trace Only for testing purposes.
Page 322 Byte Lane DATA[0:7] DATA[8:15] DATA[16:23] DATA[24:31] Driven by the MPC533 when it owns the external bus and it initiated a write transaction to a slave device. For single beat transactions, the byte lanes not selected DATA[0:31] High for the transfer by ADDR[30:31] and TSIZ[0:1] do not supply valid data.
Page 323 Indicates that the current slave does not support burst mode. Burst Inhibit: Driven by the MPC533 when the slave device is controlled by the on-chip Memory Controller. The MPC533 also asserts BI for any external master burst access to internal MPC533 memory space.
Page 324 CLKOUT output signal. All signals for the MPC533 bus interface are specified with respect to the rising edge of the external CLKOUT and are guaranteed to be sampled as inputs or changed as outputs with respect to that edge.
Page 325 4. Assert transfer start (TS) 5. Drive address and attributes 1. Receive address 2. Return data 3. Assert transfer acknowledge (TA) Figure 9-4. Basic Flow Diagram of a Single Beat Read Cycle MOTOROLA Chapter 9. External Bus Interface PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 326 Receive bus grant and bus busy negated Assert BB, drive address and assert TS ADDR[8:31] RD/WR TSIZ[0:1] BURST, BDIP Data Data is valid Figure 9-5. Single Beat Read Cycle – Basic Timing – Zero Wait States 9-10 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 327 BB, drive address and assert TS ADDR[8:31] RD/WR TSIZ[0:1] BURST, BDIP Data Wait state Data is valid Figure 9-6. Single Beat Read Cycle – Basic Timing – One Wait State MOTOROLA Chapter 9. External Bus Interface 9-11 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 328 4. Assert transfer start (TS) 5. Drive address and attributes 1. Drive data 1. Assert transfer acknowledge (TA) 1. Interrupt data driving Figure 9-7. Basic Flow Diagram of a Single Beat Write Cycle 9-12 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 329 Assert BB, drive address and assert TS ADDR[8:31] RD/WR TSIZ[0:1] BURST, BDIP Data Data is sampled by slave Figure 9-8. Single Beat Basic Write Cycle Timing – Zero Wait States MOTOROLA Chapter 9. External Bus Interface 9-13 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 330 In this case, the MPC533 attempts to initiate a transfer as in the normal case. If the bus interface receives a small port size (16 or 8 bits) indication before the transfer acknowledge to the first beat (through the internal memory controller), the MCU initiates successive transactions until the completion of the data transfer.
Page 331 Pre-discharge mode is provided for applications that use 3.3-V/5-V external memories while the MPC533 data bus pads are optimized to 2.6-V memories, and cannot tolerate more than 3.1 V. When connecting 3.3-V devices to the EBUS, and performing read and write operations, this mode should be invoked in order to avoid long term reliability issues of the data pads.
Page 332 Bus Operations When PDMCR2[PREDIS_EN] bit is set, the MPC533 will discharge the bus during the address phase of any write cycle prior to the data phase. The data bus will be discharged from up to 5 V to a level which is suitable to the low voltage drivers. In most cases, the...
Page 333 9.5.4 Burst Transfer The MPC533 uses non-wrapping burst transfers to access operands of up to 32 bytes (eight words). A non-wrapping burst access stops accessing the external device when the word address is modulo four/eight. Burst configuration is determined by the value of BURST_EN in the SIUMCR register.
Page 334 In this case, the MPC533 attempts to initiate a burst transfer as in the normal case. If the memory controller signals to the bus interface that the external device has a small port size (8 or 16 bits), and if the burst is accepted, the bus interface completes a burst of 16 or 8 beats respectively for four words.
Page 335 BDIP. The slave stops driving new data after it receives the negation of the BDIP signal at the rising edge of the clock. Burst inputs (reads) in the MPC533 are used only for instruction cycles. Data load cycles are not supported.
Page 336 Return Data Negate Burst Data in Progress (BDIP) Assert Transfer Acknowledge (TA) Drive Last Data BDIP Asserted & Assert TA Receive Data Figure 9-12. Basic Flow Diagram Of A Burst-Read Cycle 9-20 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 337 Data No Data Expected Data Data Data Data is Valid is Valid is Valid is Valid Figure 9-13. Burst-Read Cycle – 32-Bit Port Size – Zero Wait State MOTOROLA Chapter 9. External Bus Interface 9-21 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 338 Normal Late Expected Data Data Data Data Data Wait State is Valid is Valid is Valid is Valid Figure 9-14. Burst-Read Cycle – 32-Bit Port Size – One Wait State 9-22 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 339 Data Data Data Data Data is Valid is Valid is Valid is Valid Wait State Figure 9-15. Burst-Read Cycle – 32-Bit Port Size – Wait States Between Beats MOTOROLA Chapter 9. External Bus Interface 9-23 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 340 Bus Operations CLKOUT ADDR[8:31] ADDR[28:31] = 0000 RD/WR TSIZ[0:1] BURST BDIP Data[0:15] Figure 9-16. Burst-Read Cycle – 16-Bit Port Size 9-24 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 341 Negate Burst Data in Progress (BDIP) Assert Transfer Acknowledge (TA) Don’t Sample BDIP Asserted Next Data Stop Driving Data Figure 9-17. Basic Flow Diagram of a Burst-Write Cycle MOTOROLA Chapter 9. External Bus Interface 9-25 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 342 Data is Sampled is Sampled is Sampled is Sampled From external master Figure 9-18. Burst-Write Cycle, 32-Bit Port Size, Zero Wait States (Only for External Master Memory Controller Service Support) 9-26 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 343 1 BURST and BDIP will be asserted for one cycle if the RCPU core requests a burst, but the USIU splits it into a sequence of normal cycles. Figure 9-19. Burst-Inhibit Read Cycle, 32-Bit Port Size (Emulated Burst) MOTOROLA Chapter 9. External Bus Interface 9-27...
Page 344 Bus Operations CLKOUT ADDR(0:29) n (n modulo 4 = 1) ADDR[30:31] RD/WR TSIZ[0:1] BURST Expects Another Data BDIP Data Figure 9-20. Non-Wrap Burst with Three Beats 9-28 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 345 (n modulo 4 = 3) ADDR[30:31] RD/WR TSIZ[0:1] BURST Is Never Asserted BDIP First and Last Beat Data DATA is Sampled Figure 9-21. Non-Wrap Burst with One Data Beat MOTOROLA Chapter 9. External Bus Interface 9-29 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 346 • Burst accesses require address bits 30 – 31 to equal zero The MPC533 performs operand transfers through its 32-bit data port. If the transfer is controlled by the internal memory controller, the MPC533 can support 8- and 16-bit data port sizes.
Page 347 — — — — — — — — — — — Half-word — — — — Word Note: “—” denotes a byte not required during that read cycle. MOTOROLA Chapter 9. External Bus Interface 9-31 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 348 9.5.7 Arbitration Phase The external bus design provides for a single bus master at any one time, either the MPC533 or an external device. One or more of the external devices on the bus can have the capability of becoming bus master for the external bus. Bus arbitration may be handled either by an external central bus arbiter or by the internal on-chip arbiter.
Page 349 BR or kept asserted for the current master to park the bus. When configured for external central arbitration, BG is an input signal to the MPC533 from the external arbiter. When the internal on-chip arbiter is used, this signal is an output from the internal arbiter to the external bus master.
Page 350 BB line negated, regardless of how many cycles have passed since the previous master relinquished the bus. Refer to Figure 9-25. Master External Bus MPC5xx Device (Slave 1) Slave 2 Figure 9-25. Master Signals Basic Connection 9-34 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 351 9.5.7.4 nternal Bus Arbiter The MPC533 can be configured at system reset to use the internal bus arbiter. In this case, the MPC533 will be parked on the bus. The parking feature allows the MPC533 to skip the bus request phase, and if BB is negated, assert BB and initiate the transaction without waiting for BG from the arbiter.
Page 352 Parked access is instruction or data access from the RCPU which is initiated on the internal bus without requesting it first in order to improve performance. Figure 9-27 illustrates the internal finite-state machine that implements the arbiter protocol. 9-36 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 353 Figure 9-27. Internal Bus Arbitration State Machine 9.5.8 Address Transfer Phase Signals Address transfer phase signals include the following: • Transfer start • Address bus • Transfer attributes MOTOROLA Chapter 9. External Bus Interface 9-37 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 354 BURST is driven by the bus master at the beginning of the bus cycle along with the address to indicate that the transfer is a burst transfer. The MPC533 supports a non-wrapping, 8-beat maximum (with 32-bit port), critical word first burst type. The maximum burst size is 32 bytes. For a 16-bit port, the burst includes 16 beats.
Page 355 Section 9.5.10, “Storage Reservation.” Refer to Section 9.5.14, “Show Cycle Transactions” for information on show cycles. Table 9-7 summarizes the pins used to define the address type. Table 9-8 lists all the definitions achieved by combining these pins. MOTOROLA Chapter 9. External Bus Interface 9-39 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 356 Bus Operations Table 9-7. Address Type Pins Function 0 Special transfer 1 Normal transfer 0 Start of transfer 1 No transfer AT[0] Must equal zero on MPC533 AT[1] 0 Supervisor mode 1 User mode AT[2] 0 Instruction 1 Data AT[3]...
Page 357 BDIP can also be used to terminate the burst cycle early. Refer to Section 9.5.4, “Burst Transfer” and Section 9.5.5, “Burst Mechanism” for more information. Refer to Section 10.9.3, “Memory Controller Base Registers (BR0–BR3)” for memory controller BDIP options. MOTOROLA Chapter 9. External Bus Interface 9-41 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 358 Refer to Figure 9-28 and Figure 9-29. 9-42 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 359 Figure 9-29. Termination Signals Protocol Timing Diagram MOTOROLA Chapter 9. External Bus Interface 9-43 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 360 The MPC533 storage reservation protocol supports a multi-level bus structure. For each local bus, storage reservation is handled by the local reservation logic.
Page 361 CLKOUT Figure 9-30. Reservation On Local Bus The MPC533 samples the CR line at the rising edge of CLKOUT. When this signal is asserted, the reservation flag is reset (negated). The external bus interface (EBI) samples the logical value of the reservation flag prior to externally starting a bus cycle initiated by the RCPU stwcx instruction.
Page 362 (negated) when an alternative master on the remote bus accesses the same location in a write cycle. If the MPC533 begins a memory cycle to the previously reserved address (located in the remote bus) as a result of an stwcx instruction, the following two cases can...
Page 363 This allows any external master to gain bus ownership. In the next clock cycle, a normal arbitration procedure occurs again. As shown in the figure, the external master did not use the bus, so the MPC533 initiates a new transfer with the same address and attributes as before.
Page 364 Bus Operations CLKOUT BG (output) Allow External Master to Gain the Bus ADDR[8:31] ADDR ADDR RD/WR TSIZ[0:1] BURST Data RETRY (input) Figure 9-32. Retry Transfer Timing – Internal Arbiter 9-48 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 365 RETRY (input) Figure 9-33. Retry Transfer Timing – External Arbiter When the MPC533 initiates a burst access, the bus interface recognizes the RETRY assertion as a retry termination only if it detects it before the first data beat was acknowledged by the slave device. When the RETRY signal is asserted as a termination...
Page 366 16-byte transfer recognizes the RETRY signal assertion as a transfer error acknowledge. In the case in which a small port size causes the MPC533 to break a bus transaction into several small transactions, terminating any transaction with RETRY causes a transfer error acknowledge.
Page 367 If an address or data error is detected internally, the MPC533 asserts TEA for one clock. TEA should be negated before the second rising edge after it is sampled asserted in order to avoid the detection of an error for the next bus cycle initiated.
Page 368 Memory Map Memory Controller 1. Returns Data Asserts CSx If In Range 1. Asserts Transfer Acknowledge (TA) 1. Receives Data Figure 9-35. Basic Flow of an External Master Read Access 9-52 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 369 Figure 9-36. Basic Flow of an External Master Write Access Figure 9-37, Figure 9-38 and Figure 9-39 describe read and write cycles from an external master accessing internal space in the MPC533. NOTE The minimum number of wait states for such access is two clocks.
Page 370 Assert BB, Drive Address and Assert TS ADDR[8:31] RD/WR TSIZ[0:1] BURST BDIP TS (input) Data TA (output) Minimum 2 Wait States Data is valid Figure 9-37. Peripheral Mode: External Master Reads from – Two Wait States 9-54 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 371 9.5.13 Contention Resolution on External Bus When the MPC533 is in slave mode, external master access to the MPC533 internal bus can be terminated with relinquish and retry in order to allow a pending internal-to-external access to be executed. The RETRY signal functions as an output that signals the external master to release the bus ownership and retry the access after one clock.
Page 372 Memory Map Memory Controller 1. Returns Data Asserts CSx If In Range 1. Asserts Transfer Acknowledge (TA) 1. Receives Data Figure 9-39. Flow of Retry of External Master Read Access 9-56 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 373 9.5.14 Show Cycle Transactions Show cycles are representations of RCPU accesses to internal devices of the MPC533. These accesses are driven externally for emulation, visibility, and debugging purposes. A show cycle can have one address phase and one data phase, or just an address phase in the case of instruction show cycles.
Page 374 — 1 = decompression on mode; • DATA[1:4] = bit pointer See Chapter 4, “Burst Buffer Controller 2 Module” and Appendix G, “MPC534 Compression Features” for more details about decompression mode. 9-58 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 375 • Two clock cycle duration • Address valid for two clock cycles • Data is valid only in the second clock cycle • STS signal only is asserted (no TA or TS) MOTOROLA Chapter 9. External Bus Interface 9-59 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 376 BR (in) BG (out) ADDR[8:31] ADDR1 ADDR2 RD/WR TSIZ[0:1] BURST Data DATA1 DATA2 Read Data Show Cycle Bus Transaction Write Data Show Cycle Bus Transaction Figure 9-42. Data Show Cycle Transaction 9-60 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 377 CS0 through CS3. CS0 also functions as the global (boot) chip-select for accessing the boot flash EEPROM. The chip select allows zero to 30 wait states. Figure 10-2 is a block diagram of the MPC533 memory controller. MOTOROLA Chapter 10.
Page 378 CS[0] bank, refer to Section 10.7, “Global (Boot) Chip-Select Operation.") A full 32-bit address decode for each memory bank is possible with 17 bits having address masking. The full 32-bit decode is available, even if all 32 address bits are not MPC533 signals connected to the external device.
Page 379 (MTS) strobe permits one master on a bus to access external memory through the chip selects on another. The memory controller functionality allows MPC533-based systems to be built with little or no glue logic. A minimal system using no glue logic is shown in Figure 10-3. In this example CS[0] is used for a 16-bit boot EPROM and CS[1] is used for a 32-bit SRAM.
Page 380 BRx and ORx registers contain the attributes specific to memory bank x. The base register contains a valid bit (V) that indicates the register information for that particular chip select is valid. 10-4 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 381 The memory controller supports burst accesses of external burstable memory. To enable bursts, clear the burst inhibit (BI) bit in the appropriate base register. Burst support is for read only. MOTOROLA Chapter 10. Memory Controller 10-5 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 382 On the other hand, this additional cycle, under certain conditions, may be compensated for by reducing the number of cycles in initial data access and sequential burst beats. 10-6 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 383 Initial access time of memory Data setup time of CPU Delays 53ns The number of clocks required therefore 4 clocks are ---------- - 2.96 1(SST Enable Clock) 3.96 17.9 required. MOTOROLA Chapter 10. Memory Controller 10-7 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 384 4-1-1-1 burst cycle with a short setup time. Short setup time creates a saving of three clock cycles with a 4-beat burst and can result in even better performance with an 8-beat burst, saving seven clock cycles. 10-8 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 385 Data 1st Data 2nd Data 3rd Data 4th Data Is Valid Is Valid Is Valid Is Valid Figure 10-5. A 4-2-2-2 Burst Read Cycle (One Wait State Between Bursts) MOTOROLA Chapter 10. Memory Controller 10-9 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 386 Figure 10-6. 4 Beat Burst Read with Short Setup Time (Zero Wait State) NOTE An extra clock cycle is required to enable short set-up time, resulting in a 4-1-1-1 cycle. 10-10 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 387 The general-purpose chip-select machine (GPCM) allows a glueless and flexible interface between the MPC533 and external SRAM, EPROM, EEPROM, ROM peripherals. When an address and address type match the values programmed in the BR and OR for one of the memory controller banks, the attributes for the memory cycle are taken from the OR and BR registers.
Page 388 10.3.1 Memory Devices Interface Example Figure 10-7 describes the basic connection between the MPC533 and a static memory device. In this case CSx is connected directly to the chip enable (CE) of the memory device. The WE/BE[0:3] lines are connected to the respective WE in the memory device where each WE/BE line corresponds to a different data byte.
Page 389 10.3.2 Peripheral Devices Interface Example Figure 10-9 illustrates the basic connection between the MPC533 and an external peripheral device. In this case CSx is connected directly to the chip enable (CE) of the memory device and the R/W line is connected to the R/W in the peripheral device. The CSx line is the strobe output for the memory access.
Page 390 (SETA = 1) and TRLX = 1, the memory controller does not support external devices that provide TA to complete the transfer with zero wait states. The minimum access duration in this case equals three clock cycles. 10-14 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 391 • Because TRLX is set, assertion of the CS and WE strobes is delayed by one clock cycle. • CS assertion is delayed an additional one quarter clock cycle because ACS = 10. MOTOROLA Chapter 10. Memory Controller 10-15 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 392 — The basic memory cycle requires two clock cycles. — Two extra clock cycles are required due to the effect of TRLX on the assertion and negation of the CS and WE strobes. 10-16 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 393 — The basic memory cycle requires two clock cycles. — One extra clock cycle is required due to the effect of TRLX on the negation of the WE/BE strobes. MOTOROLA Chapter 10. Memory Controller 10-17 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 394 For devices that require a long disconnection time from the data bus on read accesses, the bit EHTR in the corresponding OR register can be set. In this case any MPC533 access to the external bus following a read access to the referred memory bank is delayed by one clock cycle unless it is a read access to the same bank.
Page 395 Figure 10-16 shows a write access following a read access when EHTR = 1. An extra clock is inserted between the cycles. For a write cycle following a read, this is true regardless of whether both accesses are to the same region. MOTOROLA Chapter 10. Memory Controller 10-19...
Page 396 Figure 10-16. Consecutive Accesses (Write After Read, EHTR = 1) Figure 10-17 shows consecutive accesses from different banks. Because EHTR = 1 (and the accesses are to different banks), an extra clock cycle is inserted. 10-20 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 397 Figure 10-18 shows two consecutive read cycles from the same bank. Even though EHTR = 1, no extra clock cycle is inserted between the memory cycles. (In the case of two consecutive read cycles to the same region, data contention is not a concern.) MOTOROLA Chapter 10. Memory Controller 10-21...
Page 398 2 + SCY write 1/4 * clock 3/4 * clock 1/2 * clock 2 + SCY write 1/4 * clock 1/2 * clock 3/4 * clock 1/2 * clock 2 + SCY 10-22 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 399 • If LBDIP = 1 (late BDIP assertion), the BDIP signal is asserted only after the number of wait states for the first beat in a burst have elapsed. See Figure 9-13 in Chapter 9, “External Bus Interface,” as well as Section 9.5.5, “Burst Mechanism.” MOTOROLA Chapter 10. Memory Controller 10-23...
Page 400 16-bit port (PS = 10) and a 8-bit port (PS = 01) are shown in Table 10-4. This table shows which write enables are asserted (indicated with an ‘X’) for different combinations of port size and transfer size 10-24 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 401 ISB[0:2] represents the bit field in IMMR register that determines the location of the address map of the MPC533. With dual mapping, aliasing of address spaces may occur. This happens when the region is dual-mapped into a region which is also mapped into one of the four regions available in MOTOROLA Chapter 10.
Page 402 (DMBR[DME] = 1, but BRx[V] = 0). Figure 10-19 illustrates the phenomenon. MPC5xx Memory Map Physical External Memory Dual Mapping Dual-Map region Flash External CSx Figure 10-19. Aliasing Phenomenon Illustration 10-26 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 403 The memory controller will operate in this boot mode until the first write to any chip select option register (ORx).The chip select signal can be programmed to continue decoding a range of addresses after this write, provided the preferred address range is first loaded into MOTOROLA Chapter 10. Memory Controller 10-27...
Page 404 The global chip select feature is disabled by driving only the BDIS line of the RCW (FLEN, BDIS, DME = 0b010). This is shown in case 3 of Table 10-5. 10-28 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 405 If the address of any master is mapped within the internal MPC533 address space, the access will be directed to the internal device, and will be ignored by the memory controller. If the address is not mapped internally, but rather...
Page 406 When the memory controller serves an external master, the BDIP signal becomes an input signal. This signal is watched by the memory controller to detect when the burst is terminated. 10-30 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 407 WE/BE BDIP BDIP Data Data BURST BURST NOTE: The memory controller’s BDIP line is used as a burst_in_progress signal. Figure 10-20. Synchronous External Master Configuration For GPCM-Handled Memory Devices MOTOROLA Chapter 10. Memory Controller 10-31 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 408 WE/BE Data Figure 10-21. Synchronous External Master Basic Access (GPCM Controlled) NOTE Because the MPC533 has only 24 address signals, the eight most significant internal address lines are driven as 0b0000_0000, and so compared in the memory controller’s regions. 10-32...
Page 409 10.9.1 General Memory Controller Programming Notes 1. In the case of an external master that accesses an internal MPC533 module (in slave or peripheral mode), if that slave device address also matches one of the memory controller’s regions, the memory controller will not issue any CS for this access, nor will it terminate the cycle.
Page 410 The reset value is determined by the value on the internal data bus during reset (reset-configuration word). See Table 10-10 for reset value. Figure 10-23. Memory Controller Base Registers 0–3 (BR0–BR3) 10-34 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 411 0 TA generated internally by memory controller 1 TA generated by external logic. Note that programming the timing of CS/WE/OE strobes may have no meaning when this bit is set MOTOROLA Chapter 10. Memory Controller 10-35 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 412 It is recommended that this field would hold values that are the power of 2 minus 1 (e.g., 2 - 1 = 7 [0b111]). Figure 10-24. Memory Controller Option Registers 1–3 (OR0–OR3) 10-36 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 413 EHTR Extended hold time on read accesses. This bit, when asserted, inserts an idle clock cycle after a read access from the current bank and any MPC533 write accesses or read accesses to a different bank. 0 Memory controller generates normal timing 1 Memory controller generates extended hold timing Following a system reset, the EHTR bits are cleared in OR0.
Page 414 These bits are used in conjunction with the AM[11:16] bits in the DMOR. 10-38 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 415 It is recommended that this field hold values that are the power of 2 minus 1 (e.g., 2 - 1 = 7 [0b111]). Figure 10-26. Dual-Mapping Option Register (DMOR) MOTOROLA Chapter 10. Memory Controller 10-39 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 416 NOTE: Following a system reset, the ATM bits are cleared in DMOR, except the ATM2 bit. This means that only data accesses are dual mapped. Refer to the address types definition in Table 9-8. 13:31 — Reserved 10-40 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 417 — Protection for CALRAM accesses from the U-bus side (all accesses to the CALRAM from the U-bus side are blocked once the CALRAM protection bit is set) MOTOROLA Chapter 11. L-Bus to U-Bus Interface (L2U) 11-1 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 418 • Programming is done using the MPC500’s mtspr/mfspr instructions to/from implementation-specific special purpose registers. • No protection for accesses to the CALRAM module on the L-bus (CALRAM has its own protection options) 11-2 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 419 L2U Block Diagram 11.3 L2U Block Diagram Figure 11-1 shows a block diagram of the L-bus to U-bus interface as implemented in the overall MPC533 bus architecture. U-Bus Burst Buffer Controller MPC500 DMPU E-Bus Core USIU U-Bus L-Bus Reservation Interface...
Page 420 Factory test mode is a special mode of operation that allows access to the internal modules for testing. This mode is not intended for general use and is not supported for normal applications. 11-4 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 421 During each load or store access from the RCPU to the U-bus, the address is compared to the value in the region base address register of each enabled region. Any access that MOTOROLA Chapter 11. L-Bus to U-Bus Interface (L2U) 11-5 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 422 If an enabled region overlaps with the L-bus space, the DMPU ignores all accesses to addresses within the L-bus space. If an enabled region overlaps with MPC500 register addresses, the DMPU ignores any access marked as an MPC500 access. 11-6 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 423 16 Kbytes for region zero (i.e., L2U_RA0[RS] = 0x3) and the region base address is programmed to 0x1FFF(i.e., L2U_RBA0[RBA] = 0x1), then the effective base address of region zero is 0x0. See Figure 11-3. MOTOROLA Chapter 11. L-Bus to U-Bus Interface (L2U) 11-7...
Page 424 That is, the reservation loss indication comes as part of the stwcx cycle. 11.6.1 Reservation Protocol The reservation protocol operates under the following assumptions: • Each processor has at most 1 reservation flag 11-8 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 425 If an stwcx cycle has been issued at the same time, the RCPU aborts the cycle. Software must check the CR0[EQ] bit to determine if the stwcx instruction completed successfully. MOTOROLA Chapter 11. L-Bus to U-Bus Interface (L2U) 11-9...
Page 426 U-bus. The L2U samples the status of the reservation along with the U-bus cycle termination signals and it communicates to the core if the current write has been aborted by the slave with no side effects. 11-10 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 427 L-bus one clock later. L2U asserts the internal bus request signal on the U-bus for a minimum of two clocks when starting a show cycle on the U-bus. MOTOROLA Chapter 11. L-Bus to U-Bus Interface (L2U) 11-11 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 428 U-bus is asserted, the L2U does not start the show cycle. The L2U module releases the U-bus until the no-show cycle indicator is negated and then arbitrates for the U-bus again. 11-12 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 429 There will be a 1-clock turnaround because the L-bus retry information is not available in time to negate the L-bus arbitration. L2U indicates L2U registers. U-bus/E-bus refers to all destinations through the L2U interface. MOTOROLA Chapter 11. L-Bus to U-Bus Interface (L2U) 11-13 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 430 U-bus that it is a PPC register access. A user mode access, or an access marked as instruction, to L2U registers from the U-bus side will cause a data error on the U-bus. 11-14 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 431 The L2U region base address register (L2U_RBAx) defines the base address of a specific region protected by the data memory protection unit. There are four registers (x = 0...3), one for each supported region. MOTOROLA Chapter 11. L-Bus to U-Bus Interface (L2U) 11-15...
Page 432 There are four registers (x = 0...3), one for each supported region. Field — Reset 0000_0000_0000_0000 Field — — Reset 0000_0000_0000_0000 Addr SPR 824–827 Figure 11-6. L2U Region X Attribute Register (L2U_RAx) 11-16 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 433 This register also provides enable/disable control for the four DMPU regions. Field ENR0 ENR1 ENR2 ENR3 — Reset 0000_0000_0000_0000 Field — — — Reset 0000_0000_0000_0000 Addr SPR 536 Figure 11-7. L2U Global Region Attribute Register (L2U_GRA) MOTOROLA Chapter 11. L-Bus to U-Bus Interface (L2U) 11-17 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 434 10 Supervisor read/write access, user read-only access 11 Supervisor read/write access, user read/write access 22:24 — Reserved Guarded attribute 0 Not guarded from speculative accesses 1 Guarded from speculative accesses 26:31 — Reserved 11-18 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 435 — Burst-inhibited accesses to the modules on IMB3 • Support of 32-bit and 16-bit BIUs for IMB3 modules • Half and full speed operation of IMB3 bus with respect to U-bus MOTOROLA Chapter 12. U-Bus to IMB3 Bus Interface (UIMB) 12-1...
Page 436 STOP bit is 0 and the HSPEED bit is 0, the IMB clock is generated as the inversion of the internal system clock. This is the same frequency as the CLKOUT if EBDF is 0b00 – full 12-2 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 437 16-bit and 32-bit IMB modules. During a bus transaction, the slave module on the IMB signals its port size (16- or 32-bit) via an internal port size signal. MOTOROLA Chapter 12. U-Bus to IMB3 Bus Interface (UIMB) 12-3...
Page 438 The UIMB drives two signals (ILBS[0:1]) with a multiplexer select code that tells all interrupting modules on the IMB about which group of signals to drive during the next clock. See Figure 12-5. 12-4 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 439 IMB interrupt sources mapped onto 16:23 levels will drive interrupts onto IMB LVL[0:7] IMB interrupt sources mapped onto 24:31 levels will drive interrupts onto IMB LVL[0:7] MOTOROLA Chapter 12. U-Bus to IMB3 Bus Interface (UIMB) 12-5 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 440 For each of the 32 interrupt levels, a corresponding bit of the UIPEND register is set. Figure 12-4 shows how the eight interrupt lines are connected to the UIPEND register to represent 32 levels of interrupts. Figure 12-6 shows the implementation of the interrupt synchronizer. 12-6 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 441 UIMB registers. As shown in Figure 1-2, this block begins at offset 0x30 7F80 from the start of the MPC533 internal memory map (the last 128-byte sub-block of the UIMB interface memory map).
Page 442 However, once logic 0 is written to this location, any attempt to rewrite this bit to a logic 1 will have no effect. 0 IMB frequency is the same as that of the U-bus 1 IMB frequency is one half that of the U-bus 4:31 — Reserved 12-8 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 443 0:31 LVLx Pending interrupt request level. Accessible only in supervisor mode. LVLx identifies the interrupt source as UIMB LVLx, where x is the interrupt number. MOTOROLA Chapter 12. U-Bus to IMB3 Bus Interface (UIMB) 12-9 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 444 Programming Model 12-10 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 445 QADC module, not just enhanced mode of operation. For simplicity, the names QADC and QADC64E may be used interchangeably throughout this document. 13.1 QADC64E Block Diagram Figure 13-1 displays the major components of the QADC64E module on the MPC533. MOTOROLA Chapter 13. Queued Analog-to-Digital Converter Legacy Mode Operation 13-1...
Page 446 13.2 Key Features, Overview, and Quick Reference Diagrams This section gives an overview of the implementation of the QADC64E module on the MPC533. It can also be used as a quick reference guide while programming the module. 13.2.1 Features of the QADC64E Legacy Mode Operation •...
Page 447 16-bit entries are the result table, and occupy 192 16-bit address locations because the result data is readable in three data alignment formats. The QADC64E module on the MPC533 has its own memory space. Table 13-1 shows the memory map for QADC64E module A, it occupies 0x30 4800 to 0x30 4BFF.
Page 448 Configuring bits in the QADC64E module configuration register enables enhanced mode. This will be described in Section 13.3.1.3, “Switching Between Legacy and Enhanced Modes of Operation.” 13-4 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 449 (CCW) table. External Multiplex mode is software selectable, by setting the EMUX bit of control register 0, QACR0. MOTOROLA Chapter 13. Queued Analog-to-Digital Converter Legacy Mode Operation 13-5 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 450 13.3 Programming the QADC64E Registers The QADC64E has three global registers for configuring module operation: • Module configuration register (Section 13.3.1, “QADC64E Module Configuration Register (QADMCR)”), 13-6 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 451 QADC64E requires some recovery time (T in Appendix E, “Electrical Characteristics”) to stabilize the analog circuits after the stop enable bit is cleared. MOTOROLA Chapter 13. Queued Analog-to-Digital Converter Legacy Mode Operation 13-7 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 452 QADC64E saves a pointer to the next CCW in the current queue, the software can force the QADC64E to execute a different CCW by writing new queue operating modes for normal operation. The QADC64E looks at the queue operating modes, the current queue 13-8 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 453 The following information applies to accesses to address space located within the module’s 16-bit boundaries and where the response is a bus error. See Table 13-2 for more information. MOTOROLA Chapter 13. Queued Analog-to-Digital Converter Legacy Mode Operation 13-9 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 454 The bus master indicates the supervisor and user space access with the function code bits (FC[2:0]) on the IMB3. For privilege violations, refer to the Chapter 9, “External Bus Interface” to determine the consequence of a bus error cycle termination. 13-10 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 455 Figure 13-5 displays the interrupt levels on IRQ with ILBS. Refer to Chapter 12, “U-Bus to IMB3 Bus Interface (UIMB),” for more information. MOTOROLA Chapter 13. Queued Analog-to-Digital Converter Legacy Mode Operation 13-11 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 456 When the data direction bit specifies the signal to be an output, the content of the port data register is read. 13-12 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 457 All of the implemented control register fields can be read or written but reserved fields read zero and writes have no effect. Typically, they are written once when software initializes the QADC64E and are not changed afterwards. MOTOROLA Chapter 13. Queued Analog-to-Digital Converter Legacy Mode Operation 13-13 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 458 0 Disable the pause interrupt associated with queue 1 1 Enable an interrupt after the conversion of the sample requested by a CCW in queue 1 which has the pause bit set 13-14 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 459 External trigger falling edge continuous-scan mode 10100 Periodic timer continuous-scan mode: time = QCLK period x 2 10101 Periodic timer continuous-scan mode: time = QCLK period x 2 MOTOROLA Chapter 13. Queued Analog-to-Digital Converter Legacy Mode Operation 13-15 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 460 0 Disable the pause interrupt associated with queue 2 1 Enable an interrupt after the conversion of the sample requested by a CCW in queue 2 which has the pause bit set 13-16 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 461 Disabled mode, conversions do not occur 00001 Software triggered single-scan mode (started with SSE2) 00010 External trigger rising edge single-scan mode 00011 External trigger falling edge single-scan mode MOTOROLA Chapter 13. Queued Analog-to-Digital Converter Legacy Mode Operation 13-17 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 462 Periodic timer continuous-scan mode: time = QCLK period x 2 11111 Reserved mode NOTE If BQ2 was assigned to the CCW that queue 1 is currently working on, then that conversion is completed before BQ2 takes effect. 13-18 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 463 Field CF1 PF2 TOR1 TOR2 SRESET 0000_0000_0000_0000 Addr 0x30 4810 (QASR0_A) Figure 13-10. Status Register 0 (QASR0) MOTOROLA Chapter 13. Queued Analog-to-Digital Converter Legacy Mode Operation 13-19 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 464 1 = queue 1 has reached a pause (or gate closed before end-of-queue in gated mode) Refer to Table 13-10 for a summary of pause response in all scan modes. 13-20 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 465 0 = queue 2 has not reached a pause 1 = queue 2 has reached a pause Refer to Table 13-10 for a summary of pause response in all scan modes. MOTOROLA Chapter 13. Queued Analog-to-Digital Converter Legacy Mode Operation 13-21 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 466 Once set, only software or reset can clear TOR2. 0 = No unexpected queue 2 trigger events have occurred 1 = At least one unexpected queue 2 trigger event has occurred 13-22 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 467 External Trigger Single-scan Pauses External Trigger Continuous-scan Pauses Periodic/Interval Timer Trigger Single-scan Pauses Periodic/Interval Timer Continuous-scan Pauses Software Initiated Single-scan Continues Software Initiated Continuous-scan Continues MOTOROLA Chapter 13. Queued Analog-to-Digital Converter Legacy Mode Operation 13-23 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 468 CCW executed from that queue had the pause bit set. The QADC64E does not execute any CCWs from the paused queue until a trigger event occurs. Consequently, the QADC64E can service queue 2 while queue 1 is paused. 13-24 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 469 As a result, the queue status can show queue 1 active, queue 2 idle, even though neither queue is being executed during freeze. MOTOROLA Chapter 13. Queued Analog-to-Digital Converter Legacy Mode Operation 13-25...
Page 470 CCW word are read/write data, where they may be written when the software initializes the QADC64E. The remaining 6-bits are unimplemented so these read as zeros, and write operations have no effect. Each location in the CCW table 13-26 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 471 The queue operating mode determines what type of trigger event causes queue execution to begin. A MOTOROLA Chapter 13. Queued Analog-to-Digital Converter Legacy Mode Operation 13-27 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 472 • The end-of-queue 1 is implied by the beginning of queue 2, which is specified in the BQ2 field in QACR2 • The physical end of the queue RAM space defines the end of either queue 13-28 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 473 IMB3 Interface” for more information. Field — CHAN[5:0] SRESET Unaffected Addr 0x30 4A00 – 0x30 4A7F, 0x30 4E00 – 0x30 4E7F Figure 13-14. Conversion Command Word Table (CCW) MOTOROLA Chapter 13. Queued Analog-to-Digital Converter Legacy Mode Operation 13-29 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 474 QADC64E after completing an analog conversion specified by the corresponding CCW table entry. Software can read or write the result word table, but in normal operation, the software reads the result word table to obtain analog conversions from the QADC64E. 13-30 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 475 The three result data formats are produced by routing the RAM bits onto the data bus. The software chooses among the three formats by reading the result at the memory address which produces the desired data alignment. MOTOROLA Chapter 13. Queued Analog-to-Digital Converter Legacy Mode Operation 13-31 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 476 Signals from the queue control logic are fed to the multiplexer and state machine. The end of convert (EOC) signal and the successive-approximation register (SAR) are the result of the conversion. Figure 13-18 shows a block diagram of the QADC64E analog subsystem. 13-32 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 477 2.0-MHz QCLK). If the maximum final sample time period of 16 QCLKs is selected, the total conversion time is 28 QCLKs or 14 µs (with a 2.0-MHz QCLK) Figure 13-19 illustrates the timing for conversions. MOTOROLA Chapter 13. Queued Analog-to-Digital Converter Legacy Mode Operation 13-33 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 478 QCLKs in bypass mode for high frequency operation is not recommended. Sample Time Resolution N cycles: Time 10 cycles (2, 4, 8, 16) QCLK Sample Successive Approximation Resolution Time Sequence Figure 13-20. Bypass Mode Conversion Timing 13-34 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 479 DAC array produces a voltage level higher or lower than the sampled input. The comparator output feeds into the SAR which accumulates the A/D conversion result sequentially, beginning with the Msb. MOTOROLA Chapter 13. Queued Analog-to-Digital Converter Legacy Mode Operation 13-35 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 480 13.5.1 Queue Priority Queue 1 has priority over queue 2 execution. The following cases show the conditions under which queue 1 asserts its priority: 13-36 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 481 Figure 13-21 shows the CCW format and an example of using pause to create sub-queues. Queue 1 is shown with four CCWs in each sub-queue and queue 2 has two CCWs in each sub-queue. MOTOROLA Chapter 13. Queued Analog-to-Digital Converter Legacy Mode Operation 13-37 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 482 CCW, which is the beginning of the next sub-queue. A sub-queue cannot be executed a second time before the overall queue execution has been completed. Refer to Section 13.3.7, “Control Register 2 (QACR2),” for more information. 13-38 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 483 However, since the end-of-queue condition is recognized, the completion flag is also set and the queue status becomes idle, not paused. Examples of this situation include: MOTOROLA Chapter 13. Queued Analog-to-Digital Converter Legacy Mode Operation 13-39 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 484 When both queue 1 and queue 2 are disabled, wait states are not encountered for IMB3 accesses of the RAM. When both queues are disabled, it is safe to change the QCLK prescaler values. 13-40 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 485 In the software-initiated single-scan mode, the writing of a one to the single-scan enable bit causes the QADC64E to internally generate a trigger event and the queue execution begins MOTOROLA Chapter 13. Queued Analog-to-Digital Converter Legacy Mode Operation 13-41 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 486 The external trigger single-scan mode is useful when the input trigger rate can exceed the queue execution rate. Analog samples can be taken in sync with an external event, even 13-42 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 487 The QADC64E automatically performs the conversions in the queue until a pause or an end-of-queue condition is encountered. When a pause occurs, queue execution stops until MOTOROLA Chapter 13. Queued Analog-to-Digital Converter Legacy Mode Operation 13-43 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 488 In the case of the software-initiated continuous-scan mode, the trigger event is generated internally and queue execution begins immediately. In the other continuous-scan queue 13-44 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 489 The short interval of time between a queue 1 completion and the subsequent trigger event is not sufficient to allow queue 2 execution to begin. MOTOROLA Chapter 13. Queued Analog-to-Digital Converter Legacy Mode Operation 13-45 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 490 If the gate remains open and the completion flag is not cleared, when the queue completes 13-46 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 491 The software can use the periodic interrupt to obtain non-analog inputs as well, such as contact closures, as part of a periodic look at all inputs. MOTOROLA Chapter 13. Queued Analog-to-Digital Converter Legacy Mode Operation 13-47 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 492 QCLK signal. At the beginning of the high phase, the 5-bit counter is loaded with the 5-bit PSH value. When the zero detector finds that the high phase is 13-48 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 493 Figure 13-23 and Table 13-22 also show the conversion time calculated for a single conversion in a queue. For other MCU IMB3 clock frequencies and other input sample times, the same calculations can be made. MOTOROLA Chapter 13. Queued Analog-to-Digital Converter Legacy Mode Operation 13-49 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 494 • Both queue 1 and queue 2 are programmed to any mode which does not use the periodic/interval timer • IMB3 system reset or the master reset is asserted • Stop mode is selected • Freeze mode is selected 13-50 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 495 BIU components consist of • IMB3 buffers • Address match and module select logic • The BIU state machine • Clock prescaler logic MOTOROLA Chapter 13. Queued Analog-to-Digital Converter Legacy Mode Operation 13-51 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 496 Figure 13-24 shows the three bus cycles which are implemented by the QADC64E. The following paragraphs describe how the three types of accesses are used, including misaligned 16-bit and 32-bit accesses. 13-52 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 497 16-bit read or write of an odd address obtains or provides the lower half of one QADC64E location, and the upper half of the following QADC64E location. MOTOROLA Chapter 13. Queued Analog-to-Digital Converter Legacy Mode Operation 13-53 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 498 1 and queue 2. In some of the situations, CCW C2 is presumed to have the pause bit set, to show the similarities of pause and end-of-queue as terminations of queue execution. Trigger events are described in Table 13-14. 13-54 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 499 The trigger overrun error status bit is set, and otherwise, the premature trigger event is ignored. A trigger event MOTOROLA Chapter 13. Queued Analog-to-Digital Converter Legacy Mode Operation 13-55...
Page 500 T1 T1 TOR1 TOR1 TOR1 TOR2 TOR2 IDLE IDLE IDLE ACTIVE ACTIVE IDLE IDLE ACTIVE 1000 1000 0000 0010 0000 QADC S2 Figure 13-26. CCW Priority Situation 2 13-56 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 501 Situation S5 (Figure 13-29) shows that when multiple queue 2 trigger events are detected while queue 1 is busy, the trigger overrun error bit is set, but queue 1 execution is not MOTOROLA Chapter 13. Queued Analog-to-Digital Converter Legacy Mode Operation 13-57...
Page 502 RES (resume) control bit is set to 0. Situation S7 (Figure 13-31) shows that when pause operation is not in use with queue 2, queue 2 suspension works the same way. 13-58 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 503 When the RES bit is set, following suspension, queue 2 resumes execution with the aborted CCW, not the first CCW in the queue. MOTOROLA Chapter 13. Queued Analog-to-Digital Converter Legacy Mode Operation 13-59...
Page 504 2 were being executed when a new trigger event occurs. Trigger overrun on queue 2 thus permits the software to know that queue 1 is taking up so much QADC64E time that queue 2 trigger events are being lost. 13-60 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 505 1 suspending queue 2. After the freeze condition is removed, the QADC64E continues queue execution with the next CCW in sequence. MOTOROLA Chapter 13. Queued Analog-to-Digital Converter Legacy Mode Operation 13-61 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 506 Figure 13-36. CCW Freeze Situation 12 FREEZE QADC S13 Figure 13-37. CCW Freeze Situation 13 (TRIGGERS IGNORED) FREEZE T1 T1 QADC S14 T2 T2 Figure 13-38. CCW Freeze Situation 14 13-62 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 507 (Triggers Ignored) FREEZE QADC S17 Figure 13-41. CCW Freeze Situation 17 FREEZE (Trigger Captured, Response Delayed After Freeze) QADC S18 Figure 13-42. CCW Freeze Situation 18 MOTOROLA Chapter 13. Queued Analog-to-Digital Converter Legacy Mode Operation 13-63 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 508 Conversion time is >= 14 QCLKS Time between triggers QCLK Trig1 LAST CCW1 CCW2 CCW0 CCW1 LAST CCW0 CWPQ1 Q1 RES Figure 13-44. External Trigger Mode (Positive Edge) Timing with Pause 13-64 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 509 When the gate closes the active conversion completes before the queue goes idle. When Q1 completes both the CF1 bit sets and the SSE bit clears. MOTOROLA Chapter 13. Queued Analog-to-Digital Converter Legacy Mode Operation 13-65 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 510 At the end of Q1,the completion flag CF1 sets and the queue restarts. Also, note that if the queue starts a second time and completes, the trigger overrun flag TOR1 sets. 13-66 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 511 (V and low voltage input (V ) requirements. Refer to Appendix E, “Electrical Characteristics” for more information on voltage requirements. MOTOROLA Chapter 13. Queued Analog-to-Digital Converter Legacy Mode Operation 13-67 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 512 V ) define the limits of the analog reference voltages (V and V ) and of the analog multiplexer inputs. Figure 13-47 is a diagram of the analog input circuitry. 13-68 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 513 10-bit conversion value of 0x3FE. At the bottom of the signal range, is 15 mV higher than V , resulting in a minimum obtainable 10-bit conversion value of three. MOTOROLA Chapter 13. Queued Analog-to-Digital Converter Legacy Mode Operation 13-69 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 514 If multiple high precision analog circuits are locally employed (i.e., two A/D converters), the analog supplies should be isolated from each other as sharing supplies introduces the potential for interference between analog circuits. 13-70 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 515 • Non-minimum traces should be utilized for connecting bypass capacitors and filters to their corresponding ground/power points. • Distance for trace runs should be minimized where possible MOTOROLA Chapter 13. Queued Analog-to-Digital Converter Legacy Mode Operation 13-71 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 516 Ideally, that capacitor should be as large as possible (within the practical range 13-72 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 517 The following paragraphs provide a simplified description of the interaction between the QADC64E and the external circuitry. This circuitry is assumed to be a simple RC low-pass MOTOROLA Chapter 13. Queued Analog-to-Digital Converter Legacy Mode Operation 13-73 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 518 QADC64E analog input signal through a separate multiplexer chip. Also, an example of an analog signal source connected directly to a QADC64E analog input channel is displayed. 13-74 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 519 0.01 µF SOURCE C FILTER C SAMP C PCB QADC64E EXT MUX EX Typical Value typically 10KΩ–20KΩ FILTER Figure 13-51. External Multiplexing of Analog Signal Sources MOTOROLA Chapter 13. Queued Analog-to-Digital Converter Legacy Mode Operation 13-75 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 520 A series resistor limits the current to a signal, therefore input leakage acting through a large source impedance can degrade A/D accuracy. The maximum input leakage current is specified in Appendix E, “Electrical Characteristics.” Input leakage is greater at higher 13-76 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 521 Under stress conditions, current injected on an adjacent signal can cause errors on the selected channel by developing a voltage drop across the selected channel’s impedances. MOTOROLA Chapter 13. Queued Analog-to-Digital Converter Legacy Mode Operation 13-77 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 522 = Adjustable voltage source STRESS = Parasitic PNP emitter/base voltage (refer to V in Appendix E, “Electrical Characteristics”) NEGCLAMP = Parasitic NPN base/emitter voltage (refer to V in Appendix E, “Electrical Characteristics”) NEGCLAMP 13-78 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 523 Also, suitable source impedances should be selected to meet design goals and minimize the effect of stress conditions. MOTOROLA Chapter 13. Queued Analog-to-Digital Converter Legacy Mode Operation 13-79 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 524 QADC64E Integration Requirements 13-80 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 525 Queued Analog-to-Digital Converter Enhanced Mode Operation The queued analog-to-digital converter (QADC) module on the the MPC533 deviceis a 10-bit, unipolar, successive approximation converter. The module can be configured to operate in one of two modes, legacy mode (for MPC555 compatibility) and enhanced mode.
Page 526 14.2 Key Features, Overview and Quick Reference Diagrams This section gives an overview of the implementation of the QADC64E module on the MPC533. It can also be used for a quick reference while programming the module. 14.2.1 Features of the QADC64E Enhanced Mode Operation •...
Page 527 16-bit entries are the result table, and occupy 192 16-bit address locations because the result data is readable in three data alignment formats. The QADC64E module on the MPC533 has its own memory space. Table 14-1 shows the memory map for QADC64E module A, it occupies 0x30 4800 to 0x30 4BFF.
Page 528 0x30 4AFF 0x30 4B00- SIGN SIGNED LEFT JUSTIFIED 00 0000 Results 0x30 4B7F 0x30 4B80 UNSIGNED LEFT JUSTIFIED 00 0000 Results 0x30 4BFF Registers are accessible only as supervisor data space. 14-4 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 529 Key Features, Overview and Quick Reference Diagrams Accesses to supervisor-only data space is permitted only when the bus master is operating in supervisor access mode. Assignable data space can be either restricted to supervisor-only access or unrestricted to both supervisor and user data space addresses. See Section 14.3.1.4, “Supervisor/Unrestricted Address Space.”...
Page 530 QADC. The QADC provides three multiplexer address signals – MA[0], MA[1], MA[2] – to select one of the multiplexer chips. These outputs are the multiplexer control lines and they are connected to all external multiplexer chips. 14-6 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 531 Programming the QADC64E Registers AN[0] V SSA ANALOG POWER AN[1] V DDA AN[2] AN[3] AltRef AN[4] AN[5] ANALOG REFERENCES AN[6] V RL AN[7] AN[8] AN[9] AN[10] AN[11] AN[12] AN[13] AN[14] AN[15] AN[16] QADC AN[17] AN[18] ANALOG ANALOG AN[19] DIGITAL AN[52]/MA[0]/PQA[0] MULTIPLEXER AN[20] CONVERTER...
Page 532 QADC64E module, determine the privilege level required to access most registers and master/slave operation. Field STOP FRZ — LOCK FLIP SUPV — SRESET 0000_0000 000_0000 Addr 0x30 4800 (QADCMCR_A) Figure 14-4. Module Configuration Register (QADCMCR) 14-8 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 533 Programming the QADC64E Registers Table 14-3. QADCMCR Bit Descriptions Bits Name Description STOP Stop Enable — Refer to Section 14.3.1.1, “Low Power Stop Mode” for more information. 0 Disable stop mode 1 Enable stop mode Freeze Enable — Refer to Section 14.3.1.2, “Freeze Mode” for more information. 0 Ignores the IMB3 internal FREEZE signal 1 Finish any conversion in progress, then freeze —...
Page 534 LOCK bit is clear, indicating that the module is locked in legacy mode. In order to change the value of the FLIP bit, the operating mode must first be unlocked by setting the 14-10 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 535 Programming the QADC64E Registers LOCK bit. Only then can the FLIP bit be changed. Finally, the LOCK bit must be cleared again to protect the state of the FLIP bit from future writes. 1. Write LOCK = 1 to unlock operating mode bit. 2.
Page 536 QADCINT specifies the priority level of QADC64E interrupt requests. The interrupt level for queue 1 and queue 2 may be different. The interrupt register is read/write accessible in supervisor data space only. The implemented interrupt register fields can be read and 14-12 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 537 Programming the QADC64E Registers written, reserved bits read zero and writes have no effect. They are typically written once when the software initializes the QADC64E, and not changed afterwards. Field IRL1 IRL2 — SRESET 0000_0000_0000_0000 Addr 0x30 4804 (QADCINT_A) Figure 14-5. QADC Interrupt Register (QADCINT) Table 14-5.
Page 538 DDR bits are not set to one on signals used for analog inputs. When the DDR bit is set to one and the signal is selected for analog conversion, the voltage sampled is that of the output digital driver as influenced by the load. 14-14 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 539 Programming the QADC64E Registers NOTE Caution should be exercised when mixing digital and analog inputs. This should be isolated as much as possible. Rise and fall times should be as large as possible to minimize AC coupling effects. There are two special cases to consider for the digital I/O port operation. When QACR0[EMUX] bit is set, enabling external multiplexing, the data direction register settings are ignored for the bits corresponding to PORTQA[2:0], which are the three multiplexed address output signals, MA[2:0].
Page 540 1010110 1110110 0010111 0110111 1010111 1110111 0011000 0111000 1011000 1111000 0011001 0111001 1011001 1111001 0011010 0111010 1011010 1111010 0011011 0111011 1011011 1111011 0011100 0111100 1011100 1111100 0011101 0111101 1011101 1111101 14-16 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 541 Programming the QADC64E Registers Table 14-8. Prescaler f Divide-by Values (continued) SYSCLK Prescaler Prescaler Prescaler Prescaler SYSCLK SYSCLK SYSCLK SYSCLK [6:0] [6:0] [6:0] [6:0] 0011110 0111110 1011110 1111110 0011111 0111111 1011111 1111111 14.3.6 Control Register 1 Control register 1 is the mode control register for the operation of queue 1. The applications software defines the queue operating mode for the queue, and may enable a completion and/or pause interrupt.
Page 542 Periodic timer continuous-scan mode: time = QCLK period x 2 11010 Periodic timer continuous-scan mode: time = QCLK period x 2 11011 Periodic timer continuous-scan mode: time = QCLK period x 2 14-18 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 543 Programming the QADC64E Registers Table 14-10. Queue 1 Operating Modes (continued) MQ1[3:7] Operating Modes 11100 Periodic timer continuous-scan mode: time = QCLK period x 2 11101 Periodic timer continuous-scan mode: time = QCLK period x 2 11110 Periodic l timer continuous-scan mode: time = QCLK period x 2 11111 External gated continuous-scan mode 14.3.7...
Page 544 Interval timer single-scan mode: time = QCLK period x 2 00110 Interval timer single-scan mode: time = QCLK period x 2 00111 Interval timer single-scan mode: time = QCLK period x 2 14-20 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 545 Programming the QADC64E Registers Table 14-12. Queue 2 Operating Modes (continued) MQ2[3:7] Operating Modes 01000 Interval timer single-scan mode: time = QCLK period x 2 01001 Interval timer single-scan mode: time = QCLK period x 2 01010 Interval timer single-scan mode: time = QCLK period x 2 01011 Interval timer single-scan mode: time = QCLK period x 2 01100...
Page 546 QADC64E is finished with a queue 1 scan. The software acknowledges that it has detected the completion flag being set by writing a zero to the completion flag after the bit was read as a one. 14-22 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 547 Programming the QADC64E Registers Table 14-13. QASR0 Bit Descriptions (continued) Bits Name Description Queue 1 Pause Flag — PF1 indicates that a queue 1 scan has reached a pause. PF1 is set by the QADC64E when the current queue 1 CCW has the pause bit set, the selected input channel has been converted, and the result has been stored in the result table.
Page 548 0 No unexpected queue 1 trigger events have occurred 1 At least one unexpected queue 1 trigger event has occurred (or queue 1 reaches an end-of-queue condition for the second time in gated mode) 14-24 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 549 Programming the QADC64E Registers Table 14-13. QASR0 Bit Descriptions (continued) Bits Name Description TOR2 Queue 2 Trigger Overrun — TOR2 indicates that an unexpected trigger event has occurred for queue 2. TOR2 can be set when queue 2 is in the active, suspended, and trigger pending states.
Page 550 The idle state occurs when a queue is disabled, when a queue is in a reserved mode, or when a queue is in a valid queue operating mode awaiting a trigger event to initiate queue execution. 14-26 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 551 Programming the QADC64E Registers A queue is in the active state when a valid queue operating mode is selected, when the selected trigger event has occurred, or when the QADC64E is performing a conversion specified by a CCW from that queue. Only one queue can be active at a time.
Page 552 10-bits of each entry are implemented. A CCW can be programmed by the software to request a conversion of one analog input channel. The CCW table is written 14-28 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 553 Programming the QADC64E Registers by software and is not modified by the QADC64E. Each CCW requests the conversion of an analog channel to a digital result. The CCW specifies the analog channel number, the input sample time, and whether the queue is to pause after the current CCW. The ten implemented bits of the CCW word are read/write data, where they may be written when the software initializes the QADC64E.
Page 554 A scan sequence may be initiated by the following: • A software command • Expiration of the periodic/interval timer • External trigger signal • External gated signal (queue 1 only) 14-30 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 555 Programming the QADC64E Registers The software also specifies whether the QADC64E is to perform a single pass through the queue or is to scan continuously. When a single-scan mode is selected, the software selects the queue operating mode and sets the single-scan enable bit. When a continuous-scan mode is selected, the queue remains active in the selected queue operating mode after the QADC64E completes each queue scan sequence.
Page 556 Alternate Reference Enabled — Setting REF high in the CCW enables the use of an alternate reference. 0 VRH is used as high reference 1 AltRef signal is used as the high reference 14-32 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 557 Programming the QADC64E Registers Table 14-17. CCW Bit Descriptions (continued) Bits Name Description Input Sample Time — The IST field allows software to specify the length of the sample window. Provision is made to vary the input sample time, through software control, to offer flexibility in the source impedance of the circuitry providing the QADC64E analog channel inputs.
Page 558 • Left justified, with the most significant bit inverted to form a sign bit, and zeros in the unused lower order bits • Left justified, with zeros in the lower order unused bits 14-34 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 559 Programming the QADC64E Registers The left justified, signed format corresponds to a half-scale, offset binary, two’s complement data format. The data is routed onto the IMB3 according to the selected format. The address used to access the table determines the data alignment format. All write operations to the result word table are right justified.
Page 560 During the final sampling period the amplifier is bypassed, and the multiplexer input charges the sample capacitor array directly for improved accuracy. During the resolution 14-36 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 561 Analog Subsystem period, the voltage in the sample capacitor is converted to a digital value and stored in the SAR. Initial sample time is fixed at two QCLK cycles. Final sample time can be two or eight QCLK cycles, depending on the value of the IST field in the CCW. Resolution time is ten QCLK cycles.
Page 562 IST indicates the desired sample time. The end of conversion (EOC) signal notifies the queue control logic that a result is available for storage in the result RAM. 14-38 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 563 Digital Subsystem 14.5 Digital Subsystem The digital control subsystem includes the control logic to sequence the conversion activity, the clock and periodic/interval timer, control and status registers, the conversion command word table RAM, and the result word table RAM. The central element for control of the QADC64E conversions is the 64-entry CCW table. Each CCW specifies the conversion of one input channel.
Page 564 1, a separate rising edge is required on the external trigger signal after every pause to begin the execution of each sub-queue (refer to Figure 14-21). Refer to Section 14.5.4, “Scan Modes” for information on different scan modes. 14-40 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 565 Digital Subsystem The choice of single-scan or continuous-scan applies to the full queue, and is not applied to each sub-queue. Once a sub-queue is initiated, each CCW is executed sequentially until the last CCW in the sub-queue is executed and the pause state is entered. Execution can only continue with the next CCW, which is the beginning of the next sub-queue.
Page 566 • Disabled and reserved mode • Single-scan modes — Software initiated single-scan mode — External trigger single-scan mode — External gated single-scan mode — Periodic/Interval timer single-scan mode • Continuous-scan modes 14-42 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 567 Digital Subsystem — Software initiated continuous-scan mode — External trigger continuous-scan mode — External gated continuous-scan mode — Periodic/Interval timer continuous-scan mode 14.5.4.1 Disabled Mode When the disabled mode is selected, the queue is not active. Trigger events cannot initiate queue execution.
Page 568 The software initiated single-scan mode is useful in the following applications: • Allows software complete control of the queue execution • Allows the software to easily alternate between several queue sequences. 14-44 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 569 Digital Subsystem 14.5.4.3.2 External Trigger Single-Scan Mode The external trigger single-scan mode is available on both queue 1 and queue 2. The software programs the polarity of the external trigger edge that is to be detected, either a rising or a falling edge. The software must enable the scan to occur by setting the single-scan enable bit for the queue.
Page 570 • When the interrupt rate in the periodic/interval timer continuous-scan mode would be too high • In sensitive battery applications, where the single-scan mode uses less power than the software initiated continuous-scan mode 14-46 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 571 Digital Subsystem 14.5.4.4 Continuous-Scan Modes When the application software wants to execute multiple passes through a sequence of conversions defined by a queue, a continuous-scan queue operating mode is selected. By programming the MQ1 field in QACR1 or the MQ2 field in QACR2, the following software initiated modes can be selected: •...
Page 572 Some applications need to synchronize the sampling of analog channels to external events. There are cases when it is not possible to use software initiation of the queue scan sequence, since interrupt response times vary. 14-48 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 573 Digital Subsystem 14.5.4.4.3 External Gated Continuous-Scan Mode The QADC64E provides external gating for queue 1 only. When external gated continuous-scan mode is selected, the input level on the associated external trigger signal enables and disables queue execution. The polarity of the external gated signal is fixed so a high level opens the gate and a low level closes the gate.
Page 574 A change in the prescaler value while a conversion is in progress is likely to corrupt the result from any conversion in progress. Therefore, any prescaler write operation should be done only when both queues are in the disabled modes. 14-50 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 575 Digital Subsystem QCLK Clock System Clock (F Generate Prescaler Rate Selection (from Control Register 0) QADC Clock / ÷2 to F / ÷40 ) A/D Converter SAR Control Input Sample Time State Machine (From CCW) SAR[9:0] Binary Counter 2 10 2 16 2 17 2 11 2 12...
Page 576 When the internal FREEZE line is negated, the timer counter starts counting from the beginning. Refer to Section 14.5.7, “Configuration And Control Using the IMB3 Interface” for more information. 14-52 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 577 Digital Subsystem 14.5.7 Configuration And Control Using the IMB3 Interface The QADC64E module communicates with other microcontroller modules via the IMB3. The QADC64E bus interface unit (BIU) coordinates IMB3 activity with internal QADC64E bus activity. This section describes the operation of the BIU, IMB3 read/write accesses to QADC64E memory locations, module configuration, and general-purpose I/O operation.
Page 578 QADC64E locations is accessed. The first bus cycle is treated by the QADC64E as an 8-bit read or write of an odd address. The second cycle is an 8-bit read or write of an even 14-54 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 579 Trigger and Queue Interaction Examples address. The QADC64E address space is organized into 16-bit even address locations, so a 16-bit read or write of an odd address obtains or provides the lower half of one QADC64E location, and the upper half of the following QADC64E location. 32-bit accesses to an even address require two bus cycles to complete the access, and two full 16-bit QADC64E locations are accessed.
Page 580 Below the queue execution flows are three sets of blocks that show the status information that is made available to the software. The first two rows of status blocks show the condition of each queue as: • Idle • Active • Pause 14-56 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 581 Trigger and Queue Interaction Examples • Suspended (queue 2 only) • Trigger pending The third row of status blocks shows the 4-bit QS status register field that encodes the condition of the two queues. Two transition status cases, QS = 0011 and QS = 0111, are not shown because they exist only very briefly between stable status conditions.
Page 582 Situation S4 (Figure 14-27) shows that a queue 2 trigger event that is recognized while queue 1 is active is saved, and as soon as queue 1 is finished, queue 2 servicing begins. 14-58 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 583 Trigger and Queue Interaction Examples IDLE IDLE ACTIVE IDLE TRIGGERED ACTIVE IDLE 0000 1000 1011 0010 0000 QADC S4 Figure 14-27. CCW Priority Situation 4 Situation S5 (Figure 14-28) shows that when multiple queue 2 trigger events are detected while queue 1 is busy, the trigger overrun error bit is set, but queue 1 execution is not disturbed.
Page 584 When the RES bit is set, following suspension, queue 2 resumes execution with the aborted CCW, not the first CCW in the queue. 14-60 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 585 Trigger and Queue Interaction Examples RESUME=1 PAUSE IDLE ACTIVE ACTIVE ACTIVE IDLE IDLE IDLE ACTIVE SUSPEND ACTIVE 0000 1000 0100 0110 1010 0010 0000 QADC S8 Figure 14-31. CCW Priority Situation 8 RESUME=1 ACTIVE IDLE IDLE ACTIVE PAUSE IDLE IDLE PAUSE ACTIVE SUSPEND...
Page 586 When freeze is detected, the QADC64E completes the conversion in progress, unlike queue 1 suspending queue 2. After the freeze condition is removed, the QADC64E continues queue execution with the next CCW in sequence. 14-62 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 587 Trigger and Queue Interaction Examples Trigger events that occur during freeze are not captured. When a trigger event is pending for queue 2 before freeze begins, that trigger event is remembered when the freeze is passed. Similarly, when freeze occurs while queue 2 is suspended, after freeze, queue 2 resumes execution as soon as queue 1 is finished.
Page 588 Figure 14-39. CCW Freeze Situation 16 (TRIGGERS IGNORED) FREEZE QADC S17 Figure 14-40. CCW Freeze Situation 17 FREEZE (TRIGGER CAPTURED, RESPONSE DELAYED AFTER FREEZE) QADC S18 Figure 14-41. CCW Freeze Situation 18 14-64 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 589 Trigger and Queue Interaction Examples FREEZE QADC S19 Figure 14-42. CCW Freeze Situation 19 14.6.2 Conversion Timing Schemes This section contains some conversion timing examples. Example 1 below shows the timing for basic conversions where the following is assumed: • Q1 begins with CCW0 and ends with CCW3 •...
Page 590 When the gate closes and opens again the conversions start with the first CCW in Q1. When the gate closes the active conversion completes before the queue goes idle. When Q1 completes both the CF1 bit sets and the SSE bit clears. 14-66 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 591 Trigger and Queue Interaction Examples Trig1 (gate) LAST CCW1 CCW2 CCW3 CCW0 CCW1 CCW0 LAST CCW0 CCW0 CCW1 CCW2 CCW3 CCW1 CWPQ1 LAST Q1 RES Software must set SSE Software must clear PF1 Figure 14-44. Gated Mode, Single-Scan Timing Example 3 below shows the timing for conversions in gated continuous-scan mode with the same assumptions in the amended definition for the PF bit in this mode to reflect the condition that a gate closing occurred before the queue completed is a proposal under consideration at this time as example 2.
Page 592 Port A signals are connected to a digital input synchronizer during reads and may be used as general purpose digital inputs when the applied voltages meet high voltage input (V 14-68 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 593 QADC64E Integration Requirements and low voltage input (V ) requirements. Refer to Appendix E, “Electrical Characteristics” for more information on voltage requirements. The Port A signal is configured as an input or output by programming the port data direction register (DDRQA). The digital input signal states are read by the software in the upper half of the port data register when the port data direction register specifies that the signals are inputs.
Page 594 10-bit conversion value of 0x3FE. At the bottom of the signal range, is 15 mV higher than V , resulting in a minimum obtainable 10-bit conversion value of three. 14-70 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 595 QADC64E Integration Requirements .010 .020 .030 5.100 5.110 5.120 5.130 = 5.12 V, V = 0 V) Input in Volts (V QADC64E Clipping Figure 14-47. Errors Resulting from Clipping 14.7.3.1 Analog Supply Filtering and Grounding Two important factors influencing performance in analog integrated circuits are supply filtering and grounding.
Page 596 One approach is to star-point the different grounds at the power supply origin, thus keeping the ground isolated. Refer to Figure 14-48. 14-72 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 597 QADC64E Integration Requirements Supply Digital Power Analog Power Supply AGND PGND QADC64E Figure 14-48. Star-Ground at the Point of Power Supply Origin Another approach is to star-point the different grounds near the analog ground signal on the microcontroller by using small traces for connecting the non-analog grounds to the analog ground.
Page 598 Figure 14-49 is a simplified model of an input channel. Refer to this model in the following discussion of the interaction between the external circuitry and the circuitry inside the QADC64E. 14-74 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 599 QADC64E Integration Requirements Source External Filter Internal Circuit Model SAMP = Source Voltage = Source Impedance = Filter Impedance = Filter Capacitor = Internal Parasitic Capacitance = Sample Capacitor SAMP = Internal Voltage Source During Sample and Hold QADC64E Sample AMP Model Figure 14-49.
Page 600 MUXIN FILTER SOURCE FILTER 0.01 µF SOURCE MUXIN FILTER FILTER SOURCE 0.01 µF SOURCE FILTER SAMP C PCB QADC64E EXT MUX EX Figure 14-50. External Multiplexing of Analog Signal Sources 14-76 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 601 QADC64E Integration Requirements 14.7.5.2 Settling Time for the External Circuit The values for R and C in the external circuitry determine the length of time required to charge C to the source voltage level (V ). At time t = 0, V changes in Figure 14-49 while S1 is open, disconnecting the internal circuitry from the external circuitry.
Page 602 Figure 14-51 shows an active parasitic bipolar NPN transistor when an input signal is subjected to negative stress conditions. Figure 14-52 shows positive stress conditions can activate a similar PNP transistor. 14-78 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 603 QADC64E Integration Requirements STRESS INJN Signal Under STRESS Stress PARASITIC DEVICE SELECTED Adjacent ANn+1 Signal QADC64E PAR Figure 14-51. Input Signal Subjected to Negative Stress STRESS Signal Under INJP STRESS Stress PARASITIC DEVICE SELECTED Adjacent Signal QADC64E PAR Figure 14-52. Input Signal Subjected to Positive Stress The current into the signal (I or I ) under negative or positive stress is determined by...
Page 604 QADC64E inputs so that the lower accuracy inputs are adjacent to the inputs most likely to see stress conditions. Also, suitable source impedances should be selected to meet design goals and minimize the effect of stress conditions. 14-80 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 605 QADC64E Integration Requirements MOTOROLAChapter 14. Queued Analog-to-Digital Converter Enhanced Mode Operation 14-81 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 606 QADC64E Integration Requirements t – --------------------------------------------- - R SRC     V CF V SRC 1 e –   14-82 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 607 SCI, a common external baud clock source, receive and transmit buffers on one SCI. The SCIs are fully compatible with the SCI systems found on other Motorola MCUs. The dual, independent SCI, DSCI, submodule is used to communicate with external devices and other MCUs via an asynchronous serial bus.
Page 608 • Programmable master bit rates • Programmable clock polarity and phase • End-of-transmission interrupt flag • Master-master mode fault flag • Easily interfaces to simple expansion parts (A/D converters, EEPROMS, display drivers, etc.) 15-2 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 609 • Transmit data register empty flag • Transmit complete flag • Send break QSMCM-additional SCI features: • 13-bit programmable baud-rate modulus counter • Even/odd parity generation and detection MOTOROLA Chapter 15. Queued Serial Multi-Channel Module 15-3 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 610 QSMCM memory map can be divided into supervisor-only data space and assignable data space. The address offsets shown are from the base address of the QSMCM module. Refer to Figure 4-3 for a diagram of the MPC533 internal memory map. Table 15-1. QSMCM Register Map...
Page 611 The supervisor-only data space segment contains the QSMCM global registers. These registers define parameters needed by the QSMCM to integrate with the MCU. Access to these registers is permitted only when the CPU is operating in supervisor mode. MOTOROLA Chapter 15. Queued Serial Multi-Channel Module 15-5...
Page 612 The SCI receiver and transmitter should be disabled after transfers in progress are complete. The QSPI can be halted by setting the HALT bit in SPCR3 and then setting STOP after the HALTA flag is set in SPSR. 15-6 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 613 In this structure, all interrupt sources place their asserted level on a time multiplexed bus during four different time slots, with eight levels communicated per slot. The ILBS[0:1] signals indicate which group of eight are being driven on the interrupt request lines. MOTOROLA Chapter 15. Queued Serial Multi-Channel Module 15-7...
Page 614 SCI1 and 2 Int Lev Reg. [4:0] QSPI[4:0] Int Lev Reg. [4:0] SCI_1 Interrupt Interrupt SCI_2 Interrupt Level Encoder QSPI Interrupt Interrupt Level Decoder IRQ[7:0] Figure 15-3. Interrupt Hardware Block Diagram 15-8 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 615 The user can select among 32 levels. This register can be accessed only when the CPU is in supervisor mode. MOTOROLA Chapter 15. Queued Serial Multi-Channel Module 15-9...
Page 616 Interrupt level of SPI 00000lowest interrupt level request (level 0) 11111 highest interrupt level request (level 31) 15.5 QSMCM Pin Control Registers Table 15-7 lists the three QSMCM pin control registers. 15-10 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 617 Mode DDRQS Bit Bit State Pin Function Serial data input to QSPI Master Disables data input MISO DDQS[0] Disables data output Slave Serial data output from QSPI MOTOROLA Chapter 15. Queued Serial Multi-Channel Module 15-11 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 618 PQSPAR determines which of the QSPI pins, with the exception of the SCK pin, are used by the QSPI submodule, and which pins are available for general-purpose I/O. Pins may be 15-12 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 619 0 Pin is assigned QGPIO[3] in QSMCM A or J1850_TX on QSMCM B 1 Pin is assigned PCS[3] function When J1850_TX is selected, B_RXD2 becomes J1850_RX QPAPCS2 0 Pin is assigned QGPIO[2] 1 Pin is assigned PCS[2] function MOTOROLA Chapter 15. Queued Serial Multi-Channel Module 15-13 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 620 PORTSQS pin assignment register. See Section 15.5.2, “PORTQS Pin Assignment Register (PQSPAR).” — Reserved QDDPCS3 QSPI pin data direction for the pin PCS3 0 Pin direction is input 1 Pin direction is output 15-14 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 621 The queued serial peripheral interface (QSPI) is used to communicate with external devices through a synchronous serial bus. The QSPI is fully compatible with SPI systems found on other Motorola products, but has enhanced capabilities. The QSPI can perform full duplex three-wire or half duplex two-wire transfers. Several transfer rates, clocking, and interrupt-driven communication options are available.
Page 622 An inter-transfer delay of approximately 0.8 to 204 µs (using a 40-MHz IMB3 clock) can be programmed. The default delay is 17 clocks (0.425 µs at 40 MHz). Programmable delay simplifies the interface to devices that require different delays between transfers. 15-16 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 623 The address offsets shown are from the base address of the QSMCM module. Refer to Figure 4-3 for a diagram of the MPC533 internal memory map. Table 15-12. QSPI Register Map...
Page 624 QSPI operation begins. Writing a new value to SPCR0 while the QSPI is enableddisrupts operation. Field MSTR WOMQ BITS CPOL CPHA SPBR SRESET 0000 0000_0100 Addr 0x30 5018 Figure 15-11. QSPI Control Register 0 (SPCR0) 15-18 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 625 Refer to Section 15.6.5.2, “Baud Rate Selection” for more information. Table 15-14. Bits Per Transfer Bits[3:0] Bits per Transfer 0000 0001 to 0111 Reserved (defaults to 8) 1000 1001 1010 1011 1100 1101 1110 1111 MOTOROLA Chapter 15. Queued Serial Multi-Channel Module 15-19 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 626 Rewriting NEWQP in SPCR2 causes execution to restart at the designated location. Reads of SPCR2 return the current value of the register, not the buffer. 15-20 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 627 QSPI is enabled disrupts operation. Field — LOOPQ HMIE HALT SPSR* SRESET 0000_0000_0000_0000 Addr 0x30 501E Note: See bit descriptions in Table 15-18 Figure 15-14. SPCR3 — QSPI Control Register 3 MOTOROLA Chapter 15. Queued Serial Multi-Channel Module 15-21 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 628 SPCR2. If wraparound mode is enabled (WREN = 1), the SPIF is set, after completion of the command defined by ENDQP, each time the QSPI cycles through the queue. 0 QSPI is not finished 1 QSPI is finished 15-22 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 629 RAM. Receive data is information received from a serial device external to the MCU. Transmit data is information stored for transmission to an external device. Command data defines transfer parameters. Figure 15-16 shows RAM organization. MOTOROLA Chapter 15. Queued Serial Multi-Channel Module 15-23...
Page 630 RAM. Command RAM consists of 32 bytes. Each byte is divided into two fields. The peripheral chip-select field, enables peripherals for transfer. The command control field provides transfer options. 15-24 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 631 I/O. Table 15-20 identifies the QSPI pins and their functions. Register DDRQS determines whether the pins are designated as input or output. The user must initialize DDRQS for the QSPI to function correctly. MOTOROLA Chapter 15. Queued Serial Multi-Channel Module 15-25...
Page 632 The completed queue pointer (CPTQP), contained in SPSR, points to the last command executed. The end queue pointer (ENDQP), contained in SPCR2, points to the final command in the queue. 15-26 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 633 If HALT is set during the last command in the queue, the QSPI completes the last command, sets both HALTA and SPIF, and clears SPE. If the last queue command has not MOTOROLA Chapter 15. Queued Serial Multi-Channel Module 15-27...
Page 634 When the QSPI is selected, it automatically executes the next queue transfer to exchange data with the external device correctly. 15-28 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 635 QSPI is enabled for master mode operation. Any data to be transmitted should be written into transmit RAM before the QSPI is enabled. During wraparound operation, data for subsequent transmissions can be written at any time. MOTOROLA Chapter 15. Queued Serial Multi-Channel Module 15-29...
Page 636 Initialize PQSPAR, PORTQS, and DDRQS in this Order QSPI Initialization Initialize QSPI Control Registers Initialize QSPI RAM Enable QSPI MSTR = 1 ? Figure 15-18. Flowchart of QSPI Initialization Operation 15-30 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 637 Execute Programmed Delay Programmed? Execute Standard Delay Execute Serial Transfer Store Received Data In RAM Using Queue Pointer Address Figure 15-19. Flowchart of QSPI Master Operation (Part 1) MOTOROLA Chapter 15. Queued Serial Multi-Channel Module 15-31 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 638 To CPTQP Status Bits Is Continue Bit Asserted? Negate Peripheral Chip Selects Is Delay After Transfer Execute Programmed Delay Asserted? Execute Standard Delay Figure 15-20. Flowchart of QSPI Master Operation (Part 2) 15-32 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 639 Or FREEZE Set HALTA Asserted? Is Interrupt Request Interrupt Enable Bit HMIE Set? Is HALT Or FREEZE Asserted? Figure 15-21. Flowchart of QSPI Master Operation (Part 3) MOTOROLA Chapter 15. Queued Serial Multi-Channel Module 15-33 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 640 Execute Serial Transfer When SCK Received Store Received Data In RAM Using Queue Pointer Address Write Queue Pointer to CPTQP Status Bits Figure 15-22. Flowchart of QSPI Slave Operation (Part 1) 15-34 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 641 Figure 15-23. Flowchart of QSPI Slave Operation (Part 2) Normally, the SPI bus performs synchronous bidirectional transfers. The serial clock on the SPI bus master supplies the clock signal SCK to time the transfer of data. Four possible MOTOROLA Chapter 15. Queued Serial Multi-Channel Module 15-35...
Page 642 After pins are assigned and configured, write appropriate data to the command queue. If data is to be transmitted, write the data to transmit RAM. Initialize the queue pointers as appropriate. 15-36 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 643 QSPI uses a modulus counter to derive the SCK baud rate from the MCU IMB3 clock. The following expressions apply to the SCK baud rate: f SYS SCK Baud Rate ---------------------- - 2xSPBR f SYS SPBR ----------------------------------------------------------------------- 2xSCK Baud Rate Desired MOTOROLA Chapter 15. Queued Serial Multi-Channel Module 15-37 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 644 15.6.5.4 Delay After Transfer Delay after transfer can be used to provide a peripheral deselect interval. A delay can also be inserted between consecutive transfers to allow serial A/D converters to complete 15-38 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 645 To configure a peripheral chip select, set the appropriate bit in the PQSPAR, then configure the chip-select pin as an output by setting the appropriate bit in DDRQS. The value of the MOTOROLA Chapter 15. Queued Serial Multi-Channel Module 15-39...
Page 646 15.6.5.7 Optional Enhanced Peripheral Chip Selects The MPC533 have an optional on-chip decoder for the peripheral chip selects. It is enabled if any of the PCS[4:7]EN bits are enabled in the PDMCR2 register (see Table 2-6). The decode translates the normal PCS[0:3] chip selects into a 1 of 8 decode. The polarity of the new PCS outputs can be selected by the state of the PCSV bit in the PDMCR2.
Page 647 SCK is the serial clock input in slave mode and must be assigned to the QSPI for proper operation. Assertion of the active-low slave select signal SS initiates slave mode operation. MOTOROLA Chapter 15. Queued Serial Multi-Channel Module 15-41...
Page 648 Slave wraparound mode is enabled by setting the WREN bit in SPCR2. The queue can wrap to pointer address 0x0 or to the address pointed to by NEWQP, depending on the state of 15-42 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 649 CPU changes the BITS value. As mentioned above, until PCS[0]/SS is negated (brought high), the QSPI MOTOROLA Chapter 15. Queued Serial Multi-Channel Module 15-43...
Page 650 In wraparound mode, the QSPI cycles through the queue continuously. Each time the end of the queue is reached, the SPIF flag is set. If the CPU fails to clear SPIF, it remains set, 15-44 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 651 The two SCI modules are functionally equivalent, except that the SCI1 also provides 16-deep queue capabilities for the transmit and receive operations. The SCIs are fully compatible with other Motorola SCI systems. MOTOROLA Chapter 15. Queued Serial Multi-Channel Module 15-45 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 652 H (8) 7 6 5 4 3 2 1 0 L Parity Generator Transmitter Control Logic SCCxR1 CONTROL Register SCxSR STATUS Register TDRE Internal Data Bus SCI Rx SCI Interrupt Requests Request Figure 15-24. SCI Transmitter Block Diagram 15-46 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 653 Logic SCCxR1 CONTROL Register 1 SCxDR RX Buffer (READ-ONLY) SCxSR STATUS Register SCI TX SCI Interrupt Internal Requests Request Data Bus Figure 15-25. SCI Receiver Block Diagram MOTOROLA Chapter 15. Queued Serial Multi-Channel Module 15-47 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 654 QSCI1 Transmit Queue Data locations (on 0x30 504A Memory Area half-word boundary) QSCI1 Receive Queue QSCI1 Receive Queue Data locations (on 0x30 504C-6A Memory Area half-word boundary) *Reads access the RDRx; writes access the TDRx. 15-48 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 655 The CPU can read or write this register at any time. The SCI can modify the RWU bit under certain circumstances. MOTOROLA Chapter 15. Queued Serial Multi-Channel Module 15-49 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 656 Transmit complete interrupt enable 0 SCI TC interrupts disabled. 1 SCI TC interrupts enabled. Receiver interrupt enable 0 SCI RDRF and OR interrupts disabled. 1 SCI RDRF and OR interrupts enabled. 15-50 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 657 CPU has read or written the SCxDR, the newly set status bit is not cleared. Instead, SCxSR must be read again with the bit set and SCxDR must be read or written before the status bit is cleared. MOTOROLA Chapter 15. Queued Serial Multi-Channel Module 15-51...
Page 658 RAF can be used to reduce collisions in systems with multiple masters. 0 SCI receiver is idle. 1 SCI receiver is busy. 15-52 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 659 The SCxDR consists of two data registers located at the same address. The receive data register (RDRx) is a read-only register that contains data received by the SCI serial interface. Data is shifted into the receive serial shifter and is transferred to RDRx. The MOTOROLA Chapter 15. Queued Serial Multi-Channel Module 15-53...
Page 660 The TIE, TCIE, RIE, and ILIE bits in SCCxR1 enable interrupts for the conditions indicated by the TDRE, TC, RDRF, and IDLE bits in SCxSR, respectively. 15-54 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 661 — The MSB data bit can also serve as a second STOP bit. By setting this bit permanently to one, communication with other SCIs requiring two STOP bits could be accommodated. MOTOROLA Chapter 15. Queued Serial Multi-Channel Module 15-55 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 662 The PT bit in SCCxR1 selects either even (PT = 0) or odd (PT = 1) parity. PT affects received and transmitted data. The PE bit in SCCxR1 determines whether parity checking 15-56 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 663 The transmission complete (TC) flag in SCxSR shows transmitter shifter state. When TC = 0, the shifter is busy. TC is set when all shifting operations are completed. TC is not MOTOROLA Chapter 15. Queued Serial Multi-Channel Module 15-57...
Page 664 (TIE) and transmission complete interrupt enable (TCIE) bits in SCCxR1. Service routines can load the last data frame in a sequence into SCxDR, then terminate the transmission when a TDRE interrupt occurs. 15-58 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 665 1. Sample RXDx input during each RT period and maintain these samples in a serial pipeline that is three RT periods deep. 2. If RXDx is low during this RT period, go to step 1. MOTOROLA Chapter 15. Queued Serial Multi-Channel Module 15-59...
Page 666 The possibilities of noise durations greater than one bit-time are not considered in this examples. 15-60 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 667 Noise errors, parity errors, and framing errors can be detected while a data stream is being received. Although error conditions are detected as bits are received, the noise flag (NF), MOTOROLA Chapter 15. Queued Serial Multi-Channel Module 15-61...
Page 668 SCRQ[0:15]. IDLE is not set again until after at least one frame has been received (RDRF = 1). This prevents an extended idle interval from causing more than one interrupt. 15-62 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 669 Queue Operation of SCI1 for Transmit and Receive The SCI1 serial module allows for queueing on transmit and receive data frames. In the standard mode, in which the queue is disabled, the SCI1 operates as previously defined (i.e., MOTOROLA Chapter 15. Queued Serial Multi-Channel Module 15-63...
Page 670 QBHE flag in QSCI1SR is set. The interrupt is blocked by negating QBHEI. This bit refers to the queue locations SCTQ[8:15]. 0 = QBHE interrupt inhibited 1 = Queue bottom-half empty (QBHE) interrupt enabled 15-64 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 671 OR assertion is overwritten by the next received data frame, but the data in the SC1DR is not lost. 0 = The queue is empty before valid data is in the SC1DR 1 = The queue is not empty when valid data is in the SC1DR MOTOROLA Chapter 15. Queued Serial Multi-Channel Module 15-65...
Page 672 SC1DR. This field is writable in test mode only; otherwise it is read-only. From 1 (QPEND = 0b0000) to 16 (or done, QPEND = 1111) data frames can be specified. 15-66 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 673 All other bits pertaining to the queue should be ignored by software. • Programmable queue up to 16 transmits (SCTQ[0:15]) which may allow for infinite and continuous transmits. MOTOROLA Chapter 15. Queued Serial Multi-Channel Module 15-67 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 674 SCTQ[0:15]. If the queue is disabled (QTE = 0), the TC bit operates as originally designed. • When the transmit queue is enabled (QTE = 1), writes to the transmit data register (SC1DR) have no effect. 15-68 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 675 Set QBHE QTPNT = 1111? QPEND = 1111 QTWE = 1 Clear QTWE & QTHE = 0? Set QTHE, QBHE Clear QTE Figure 15-34. Queue Transmit Flow MOTOROLA Chapter 15. Queued Serial Multi-Channel Module 15-69 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 676 If Finished Transmitting, If Transmitting Greater Then Clear QTE and/or TE Than 8 Data Frames on Wrap Read QBHE=1,Write QBHE=0 Write New Data to SCTQ[8:15] DONE Figure 15-35. Queue Transmit Software Flow 15-70 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 677 QTPNT and QPEND. The italic type indicates the action just performed by hardware. Regular type indicates the actions that should be performed by software before the next event. MOTOROLA Chapter 15. Queued Serial Multi-Channel Module 15-71 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 678 Figure 15-36. Queue Transmit Example for 17 Data Bytes 15.8.7 Example SCI Transmit for 25 Data Bytes Figure 15-37 below is an example of a transmission of 25 data frames. 15-72 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 679 1001 1111 SCTQ[15] SCTQ[15] 1111 1111 Load QPEND with QTSZ Clear QTWE Reset QTPNT Write SCTQ[8] Clear QBHE Figure 15-37. Queue Transmit Example for 25 Data Frames MOTOROLA Chapter 15. Queued Serial Multi-Channel Module 15-73 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 680 • Available on a single SCI channel (SCI1) implemented by the queue receiver enable (QRE) bit set by software. When the queue is enabled, software should ignore the RDRF bit. 15-74 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 681 SCRQ[0:15]. • For receiver queue operation, NF is cleared when the SC1SR is read with NF set, followed by a read of SCRQ[0:15]. When noise occurs, the data is loaded into the MOTOROLA Chapter 15. Queued Serial Multi-Channel Module 15-75...
Page 682 (SC1DR) is still full. The data in the shifter that generated the OR assertion is overwritten by the next received data frame, but the data in the SC1DR is not lost. 15-76 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 683 Set QOR Load RX Data to SCRQ[QRPNT], Clear QTHF Increment QRPNT Set QTHF QRPNT = 1000? Clear QBHF QRPNT = 0000? Set QBHF Figure 15-39. Queue Receive Flow MOTOROLA Chapter 15. Queued Serial Multi-Channel Module 15-77 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 684 Read Status Register With QBHF = 1 Read SCRQ[8:15] Write QBHF = 0 IDLE = 1? Clear QRE and/or RE To Exit the Queue DONE Figure 15-40. Queue Receive Software Flow 15-78 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 685 0111 0111 SCRQ[8] SCRQ[8] 1000 1000 SCRQ[15] SCRQ[15] 1111 1111 Read SCRQ[0] Read SCRQ[8:15] Clear QRE/RE Clear QBHF Figure 15-41. Queue Receive Example for 17 Data Bytes MOTOROLA Chapter 15. Queued Serial Multi-Channel Module 15-79 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 686 SCI Queue Operation 15-80 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 687 Chapter 16 CAN 2.0B Controller Module The MPC533 contains three CAN 2.0B controller modules (TouCAN). Each TouCAN is a communication controller that implements the Controller Area Network (CAN) protocol, an asynchronous communications protocol used in automotive and industrial control systems. It is a high speed (one Mbit/sec), short distance, priority based protocol that can run over a variety of mediums (for example, fiber optic cable or an unshielded twisted pair of wires).
Page 688 • Support for DeviceNet™ and Smart Distributed System 16.2 External Signals The TouCAN module interface to the external CAN bus consists of two signals: CNTX0 which transmits serial data, and CNRX0 which receives serial data. 16-2 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 689 16.3.1 Tx/Rx Message Buffer Structure Figure 16-3 displays the extended (29-bit) ID message buffer structure. MOTOROLA Chapter 16. CAN 2.0B Controller Module 16-3 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 690 Length (Rx) Length (in bytes) of the Rx data stored in offset 0x6 through 0xD of the buffer.This field is written by the TouCAN module, copied from the DLC (data length code) field of the received frame. 16-4 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 691 0b1010 then only as a response to remote frame, always. When a matching remote request frame is detected, the code for such a message buffer is changed to be 0b1110. MOTOROLA Chapter 16. CAN 2.0B Controller Module 16-5 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 692 Only one serial message buffer is active at a time, and its function depends upon the operation of the TouCAN at that time. These buffers are not accessible or visible to the user. 16-6 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 693 The receive mask registers are used as acceptance masks for received frame IDs. The following masks are defined: • A global mask, used for receive buffers 0-13 • Two separate masks for buffers 14 and 15 MOTOROLA Chapter 16. CAN 2.0B Controller Module 16-7 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 694 No match for MB3 because of ID0. No match for MB2 because of ID28. No match for MB3 because of ID28, match for MB14. No match for MB14 because of ID27. Match for MB14. 16-8 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 695 The sample point indicated in Figure 16-5 is the position of the actual sample point if a single sample per bit is selected (CANCTRL1[SAMP] bit = 0). If three samples per bit are selected, the sample point indicated in Figure 16-5 marks the position of the final sample. MOTOROLA Chapter 16. CAN 2.0B Controller Module 16-9...
Page 696 • The TouCAN bit time must be programmed to be greater than or equal to nine system clocks, or correct operation is not guaranteed.The duration of the synchronization segment, SYNC_SEG, is not programmable and is fixed at one time quantum. 16-10 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 697 Each time the internal counter counts 11 consecutive recessive bits, the Tx error counter is incremented by one and the internal counter is reset to zero. When the Tx error counter reaches the value of MOTOROLA Chapter 16. CAN 2.0B Controller Module 16-11...
Page 698 The free-running timer can optionally be reset upon the reception of a frame into message buffer 0. This feature allows network time synchronization to be performed. 16-12 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 699 The control/status word of all message buffers must be written either as an active or inactive message buffer. b) All other entries in each message buffer should be initialized as required MOTOROLA Chapter 16. CAN 2.0B Controller Module 16-13...
Page 700 When this process is over and a message buffer is selected for transmission, the frame from that message buffer is transferred to the serial message buffer for transmission. 16-14 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 701 1. Write the control/status word to hold the receive buffer inactive (code = 0b0000) 2. Write the ID_HIGH and ID_LOW words 3. Write the control/status word to mark the receive message buffer as active and empty MOTOROLA Chapter 16. CAN 2.0B Controller Module 16-15 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 702 Any write access to the control/status word of a receive message buffer during the process of selecting a message buffer for reception immediately deactivates that message buffer, removing it from the reception process. 16-16 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 703 MOTOROLA Chapter 16. CAN 2.0B Controller Module 16-17 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 704 • A dominant bit is the eighth (last) bit of the error frame delimiter or overload frame delimiter 16.5 Special Operating Modes The TouCAN module has three special operating modes: • Debug mode • Low-power stop mode • Auto power save mode 16-18 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 705 • The TouCAN ignores its Rx signals and drives its Tx signals as recessive • The TouCAN loses synchronization with the CAN bus, and the STOPACK and NOTRDY bits in the module configuration register are set MOTOROLA Chapter 16. CAN 2.0B Controller Module 16-19...
Page 706 As a result, it tries to synchronize with the CAN bus, and only then does it await the conditions required for entry into low-power stop mode. 16-20 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 707 There is no distinction between transmit and receive interrupts for a particular buffer. Each of the buffers is assigned a bit in the IFLAG register. An IFLAG bit is set when the corresponding buffer completes a successful transmission/reception. An IFLAG bit is MOTOROLA Chapter 16. CAN 2.0B Controller Module 16-21...
Page 708 Figure 16-7 displays the interrupt levels on IRQ with ILBS. IMB3 CLOCK ILBS [1:0] IMB3 IRQ [7:0] 31:24 15:8 23:16 Figure 16-7. Interrupt Levels on IRQ with ILBS 16-22 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 709 16.7 Programmer’s Model Table 16-10 shows the TouCAN address map. Refer to Figure 1-2 to locate each TouCAN module in the MPC533 address map. The column labeled “Access” indicates the privilege level at which the CPU must be operating to access the register. A designation of “S” indicates that supervisor mode is required.
Page 710 See Figure 16-3 and Figure 16-4 for message buffer definitions. 0x30 7550 — 0x30 755F(B) MBUFF5 TouCAN B Message Buffer 5. See Figure 16-3 and Figure 16-4 for message buffer definitions. 16-24 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 711 See Figure 16-3 and Figure 16-4 for message buffer definitions. The last word of each of the the MBUFF arrays (address 0x..E) is reserved and may cause an RCPU exception if read. MOTOROLA Chapter 16. CAN 2.0B Controller Module 16-25...
Page 712 TouCAN Module Configuration Register (CANMCR) Field STOP FRZ — HALT NOT WAKE SOFT SUPV SELF STOP — WAKE SRESET 0101_1001_1000_0000 Addr 0x30 7480 (CANMCR_B) Figure 16-9. TouCAN Module Configuration Register (CANMCR) 16-26 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 713 TouCAN prescaler is enabled. This is a read-only bit. 0 The TouCAN has exited debug mode and the prescaler is enabled 1 The TouCAN has entered debug mode, and the prescaler is disabled MOTOROLA Chapter 16. CAN 2.0B Controller Module 16-27...
Page 714 This register is used for factory test only. 16.7.3 TouCAN Interrupt Configuration Register (CANICR) Field — ILBS — SRESET 0000_0000_00 00_1111 Addr 0x30 7484 (CANICR_B) Figure 16-10. TouCAN Interrupt Configuration Register (CANICR) 16-28 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 715 Transmit signal configuration control. This bit field controls the configuration of the CNTX0 signals. Refer to Table 16-15. 8:15 CANCTRL1 See Table 16-16 and Section 16.7.5, “Control Register 1 (CANCTRL1).” MOTOROLA Chapter 16. CAN 2.0B Controller Module 16-29 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 716 Full CMOS drive indicates that both dominant and recessive levels are driven by the chip. The CNRX1 signal is not available on the MPC533 Open drain drive indicates that only a dominant level is driven by the chip. During a recessive level, the CNTX0 signal is disabled (three stated), and the electrical level is achieved by external pull-up/pull-down devices.
Page 717 The reset value of PRESDIV is 0x00, which forces the S-clock to default to the same frequency as the system clock. The valid programmed values are 0 through 255. 8:15 CANCTRL2 See Section 16.7.7, “Control Register 2 (CANCTRL2)”. MOTOROLA Chapter 16. CAN 2.0B Controller Module 16-31 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 718 Phase Buffer Segment 2 = (PSEG2 + 1) Time Quanta 16.7.8 Free Running Timer (TIMER) Field TIMER SRESET 0000_0000_0000_0000 Addr 0x30 748A (TIMER_B) Figure 16-15. Free Running Timer Register (TIMER) 16-32 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 719 The IDE bit of a received frame is always compared to determine if the message contains a standard or extended identifier. Its location in the mask registers (bit 12) is always one, regardless of any write to this bit. MOTOROLA Chapter 16. CAN 2.0B Controller Module 16-33...
Page 720 16.7.11 Receive Buffer 15 Mask Registers (RX15MSKHI, RX15MSKLO) The receive buffer 15 mask registers have the same structure as the receive global mask registers and are used to mask buffer 15. 16-34 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 721 This register reflects various error conditions, general status, and has the enable bits for three of the TouCAN interrupt sources. The reported error conditions are those which have occurred since the last time the register was read. A read clears these bits to zero. MOTOROLA Chapter 16. CAN 2.0B Controller Module 16-35...
Page 722 FCS[1:0] bits will again reflect the bus off state. Refer to Section 16.3.4, “Error Counters” for more information on entry into and exit from the various fault confinement states. — Reserved 16-36 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 723 Bus State Error active Error passive Bus off 16.7.13 Interrupt Mask Register (IMASK) Field IMASKH IMASKL SRESET 0000_0000_0000_0000 Addr 0x30 74A2 (IMASK_B) Figure 16-20. Interrupt Mask Register (IMASK) MOTOROLA Chapter 16. CAN 2.0B Controller Module 16-37 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 724 Figure 16-22. Receive Error Counter (RXECTR), Transmit Error Counter (TXECTR) Table 16-28. RXECTR, TXECTR Bit Descriptions Bits Name Description 0:7, RXECTR, Both counters are read only, except when the TouCAN is in test or debug mode. 8:15 TXECTR 16-38 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 725 • One MIOS14 16-bit parallel port I/O submodule (MPIOSM) • Two interrupt request submodules (MIRSM) 17.1 Block Diagram Figure 17-1 is a block diagram of the MIOS14. MOTOROLA Chapter 17. Modular Input/Output Subsystem (MIOS14) 17-1 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 726 Modular I/O Bus (MIOB) (To all submodules) 6xPWMSM PWMSM21 MIRSM0/1 MCPSM MPWM21 Bus Interface Interrupt Counter Unit Submodule Prescaler Submodules MPIO32B0 IMB3 Bus MPIOSM32 MPIO32B15 Figure 17-1. MPC533 MIOS14 Block Diagram 17-2 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 727 — Six software selectable modes allowing the MDASM to perform pulse width and period measurements, PWM generation, single input capture and output compare operations as well as port functions MOTOROLA Chapter 17. Modular Input/Output Subsystem (MIOS14) 17-3 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 728 = 40 MHz with 8 bits of resolution and divide-by-4096 prescaler selection: 38.14 Hz (8.2 ms) — Programmable duty cycle from 0% to 100% — Possible interrupt generation after every period 17-4 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 729 MPWM and the port signals have a prefix of MPIO. The modulus counter clock and load signals are multiplexed with MDASM signals. The MIOS14 input and output signal names are composed of five fields according to the following convention: • “M” MOTOROLA Chapter 17. Modular Input/Output Subsystem (MIOS14) 17-5 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 730 In the MIOS14, some signals are multiplexed between submodules using the same signal names for the inputs and outputs which are connected as shown in Table 17-1. 17.3 MIOS14 Configuration The complete MIOS14 submodule and signal configuration is shown in Table 17-1. 17-6 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 731 0x30 6098 PWM, I/O MPWM MPWM PWMSM 0x30 60A0 PWM, I/O MPWM MPWM PWMSM 0x30 60A8 PWM, I/O MPWM MPWM MMCSM CB22 0x30 60B0 Clock In MDA13 MOTOROLA Chapter 17. Modular Input/Output Subsystem (MIOS14) 17-7 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 732 MPIO32 GPIO MPIO32 MPIO32 GPIO MPIO32 MPIO32 VFLS0 GPIO MPIO32 MPIO32 VFLS1 GPIO MPIO32 MPIO32 GPIO MPIO32 MPIO32 GPIO MPIO32 MPIO32 GPIO MPIO32 MPIO32 GPIO MPIO32 MPIO32 GPIO MPIO32 MPIO32 17-8 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 733 The internal bus system within the MIOS14 is called the modular I/O bus (MIOB). The MIOB makes communications possible between any submodule and the IMB3 bus master through the MBISM. The MIOB is divided into three dedicated buses: MOTOROLA Chapter 17. Modular Input/Output Subsystem (MIOS14) 17-9 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 734 • Attempted access to unimplemented 16-bit registers within the decoded register block boundary. • Attempted user access to supervisor registers • Attempted access to test registers when not in test mode • Attempted write to read-only registers 17-10 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 735 (modular I/O bus) and the IMB3. It allows the CPU to communicate with the MIOS14 submodules. 17.6.1 MIOS14 Bus Interface (MBISM) Registers Table 17-3 is the address map for the MBISM submodule. MOTOROLA Chapter 17. Modular Input/Output Subsystem (MIOS14) 17-11 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 736 0 = MIOS14 General-Purpose I/O is selected (MPIO32B[3], MPIO32B[4]) 1 = VFLS function is selected (VFLS[0:1]) 17.6.1.2 MIOS14 Vector Register (MIOS14VECT) Field — VECT — SRESET 0000_0000_0000_0000 Addr 0x30 6802 Figure 17-4. Vector Register (MIOS14VECT) 17-12 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 737 Table 17-5. MIOS14VNR Bit Descriptions Bits Name Description Module number = 0X0E on the MPC533 8:15 Version number. May change with different revisions of the device. 17.6.1.4 MIOS14 Module Configuration Register (MIOS14MCR) The MIOS14MCR register is a collection of read/write stop, freeze, reset, and supervisor bits, as well as interrupt arbitration number bits.
Page 738 — Reserved. These bits are used for the IARB (interrupt arbitration ID) field in MIOS14 implementations that use hardware interrupt arbitration. These bits are not used on MPC533. 17.7 MIOS14 Counter Prescaler Submodule (MCPSM) The MIOS14 counter prescaler submodule (MCPSM) divides the MIOS14 clock (f ) to generate the counter clock.
Page 739 • The MIOS14 counter prescaler submodule does not use the request bus. 17.7.2 Effect of RESET on MCPSM When the RESET signal is asserted, all the bits in the MCPSM status and control register are cleared. MOTOROLA Chapter 17. Modular Input/Output Subsystem (MIOS14) 17-15 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 740 MIOB is negated, the counter restart from where it was before to freeze. The FREN bit is cleared by reset. 0 MCPSM counter not frozen. 1 MCPSM counter frozen if MIOB freeze active. 17-16 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 741 16-bit up-counter register, a 16-bit modulus latch register, counter loading and interrupt flag generation logic. The contents of the modulus latch register is transferred to the counter under the following three conditions: 1. When an overflow occurs MOTOROLA Chapter 17. Modular Input/Output Subsystem (MIOS14) 17-17 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 742 8-bit Prescale 16-bit Up-Counter Reg. MMCSMCNT Mod.Register Modulus Load Load signal (MMCnL) Edge Overflow Load Detect Control 16-bit Modulus MMCSMML Latch Reg. PINL EDGN EDGP MIOB Figure 17-9. MMCSM Block Diagram 17-18 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 743 MIOS14 Modulus Counter Submodule (MMCSM) 0xFFFF Modulus Value Two’s Complement Counter Reload Figure 17-10. MMCSM Modulus Up-Counter MOTOROLA Chapter 17. Modular Input/Output Subsystem (MIOS14) 17-19 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 744 It is loaded with an 8-bit value every time the counter overflows or whenever the prescaler output is selected as the clock source. This 8-bit value is stored in the MMCSMSCR bit 17-20 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 745 The privilege level to access to the MMCSM registers depends on the MIOS14MCR SUPV bit. The privilege level is unrestricted after SRESET and can be changed to supervisor by software. MOTOROLA Chapter 17. Modular Input/Output Subsystem (MIOS14) 17-21 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 746 0x30 60BE MMCSM23 Status/Control Register (MMCSMSCR) MMCSM24 0x30 60C0 MMCSM24 Up-Counter Register (MMCSMCNT) 0x30 60C2 MMCSM24 Modulus Latch Register (MMCSMML) 0x30 60C4 MMCSM24 Status/Control Register Duplicated (MMCSMSCRD) 0x30 60C6 MMCSM24 Status/Control Register (MMCSMSCR) 17-22 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 747 The user should not write directly to the address of the MMCSMSCRD. This register’s address may be reserved for future use and should not be accessed by the software to ensure future software compatibility. MOTOROLA Chapter 17. Modular Input/Output Subsystem (MIOS14) 17-23 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 748 Table 17-16 gives the clock divide ratio according to the value of CP. Table 17-14. MMCSMCNT Edge Sensitivity EDGN EDGP Edge Sensitivity MMCSMCNT load on rising and falling edges MMCSMCNT load on falling edges MMCSMCNT load on rising edges None (disabled) 17-24 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 749 All control and status bits are contained in the MDASM status and control register. The following sections describe the MDASM in detail. A block diagram of the MDASM is shown in Figure 17-14. MOTOROLA Chapter 17. Modular Input/Output Subsystem (MIOS14) 17-25 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 750 • Flag setting and possible interrupt generation after MDASM action completion • Software selection of output pulse polarity • Software selection of totem-pole or open-drain output • Software readable output signal status 17-26 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 751 In the input modes, the edge detect circuitry triggers a capture whenever a rising or falling edge (as defined by the EDPOL bit) is applied to the input signal. The signal on the input signal is Schmitt triggered and synchronized with the MIOS14 CLOCK. MOTOROLA Chapter 17. Modular Input/Output Subsystem (MIOS14) 17-27...
Page 752 FLAG bit merely indicates to the software that the compare value can be updated. However changing modes without passing via the disable mode does not guarantee the subsequent functionality. 17-28 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 753 Reading data register B returns the value in register B2. If subsequent input capture events occur while the FLAG bit is set in the corresponding MIRSM, data registers A and B will be updated with the latest captured values and the FLAG line will remain active. MOTOROLA Chapter 17. Modular Input/Output Subsystem (MIOS14) 17-29...
Page 754 MDASMSCR register. This mode also allows the software to determine the logic level on the input signal at any time by reading the PIN bit in the MDASMSCR register. 17-30 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 755 The input pulse period is calculated by subtracting the value in data register B from the value in data register A. Figure 17-16 provides an example of how the MDASM can be used for input period measurement. MOTOROLA Chapter 17. Modular Input/Output Subsystem (MIOS14) 17-31 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 756 0x16A0 Internal Register, not accessible to software Register B1 0x1000 0x1000 0x1400 0x1400 0x16A0 0xxxxx Register B2 0xxxxx 0xxxxx 0x1000 0x1000 0x1400 0xxxxx (Ignored) Figure 17-17. MDASM Input Capture Example 17-32 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 757 The FLAG line is not affected by these ‘force’ operations. Totem pole or open-drain output circuit configurations can be selected using the WOR bit in the MDASMSCR register. MOTOROLA Chapter 17. Modular Input/Output Subsystem (MIOS14) 17-33 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 758 (A or B), thus enabling only one of the comparators. Following the first successful match on the enabled channel, the output level is fixed and remains at the same level 17-34 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 759 Frequencies are only relevant as such if the counter bus is driven by a counter as a time reference. Both channels (A and B) are used to generate one PWM output signal on the MDASM signal. MOTOROLA Chapter 17. Modular Input/Output Subsystem (MIOS14) 17-35...
Page 760 NOTE 16-bit counter bus compare only occurs when the 16-bit counter bus is updated. Figure 17-20 provides an example of how the MDASM can be used for pulse width modulation. 17-36 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 761 MDASM resolution (this count is equal to 2 A few examples of frequencies and resolutions that can be obtained are shown in Table 17-18. MOTOROLA Chapter 17. Modular Input/Output Subsystem (MIOS14) 17-37 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 762 • The MDASM is connected to all the signals in the read/write and control bus, to allow data transfer from and to the MDASM registers, and to control the MDASM in the different possible situations. 17-38 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 763 See Section 17.9.8.3, “MDASM Data B (MDASMBR) Register” for bit descriptions. 0x30 605C MDASM11 Status/Control Register Duplicated (MDASMSCRD) See Table 17-22 for bit descriptions. 0x30 605E MDASM11 Status/Control Register (MDASMSCR) See Table 17-22 for bit descriptions. MOTOROLA Chapter 17. Modular Input/Output Subsystem (MIOS14) 17-39 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 764 0x30 60E0 MDASM28 Data A Register (MDASMAR) 0x30 60E2 MDASM28 Data B Register (MDASMBR) 0x30 60E4 MDASM28 Status/Control Register Duplicated (MDASMSCRD) 0x30 60E6 MDASM28 Status/Control Register (MDASMSCR) MDASM29 0x30 60E8 MDASM29 Data A Register (MDASMAR) 17-40 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 765 NOTE: In IC, IPM, or IPWM mode, when a read to register A or B occurs at the same time as a counter bus capture into that register and the counter bus is changing value, then the counter bus capture to that register is delayed. MOTOROLA Chapter 17. Modular Input/Output Subsystem (MIOS14) 17-41...
Page 766 MDASMSCRD. This register’s address may be reserved for future use and should not be accessed by the software to ensure future software compatibility. The duplication of the SCR register allows coherent 32-bit accesses when using an RCPU. 17-42 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 767 0 The output flip-flop logic level appears on the output signal: a match on channel A sets the output signal, a match on channel B resets the output signal. The EDPOL bit is cleared by reset. MOTOROLA Chapter 17. Modular Input/Output Subsystem (MIOS14) 17-43...
Page 768 0110 — — Reserved 0111 — — Reserved 1000 — OPWM – Output pulse width modulation 1001 OPWM – Output pulse width modulation 1010 OPWM – Output pulse width modulation 17-44 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 769 40 MHz). The MWPMSM can run in a double-buffered mode, to avoid spurious update. The following sections describe the MPWMSM in detail. A block diagram of the MPWMSM is shown in Figure 17-24. MOTOROLA Chapter 17. Modular Input/Output Subsystem (MIOS14) 17-45 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 770 511, it is said to have eight bits of resolution, and so on. Resolution The term “resolution” is used in this document to define the minimum MPWMSM output increment in time units. 17-46 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 771 MIOS14 output signals. The MPWMSM includes its own counter, and thus does not use the MIOS14 counter bus set. However the MPWMSM uses the prescaled clock bus that originates in the MIOS14 counter prescaler MOTOROLA Chapter 17. Modular Input/Output Subsystem (MIOS14) 17-47...
Page 772 1), writing to the MPWMPERR will also write to the counter. The down-counter is readable at anytime. The value loaded in the down-counter corresponds to the period of the output signal. 17-48 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 773 (N ) and the value loaded in the counter (V ) is given by the MPWMSM COUNTER following equation: PWMO • N • V MCPSM MPWMSM COUNTER MOTOROLA Chapter 17. Modular Input/Output Subsystem (MIOS14) 17-49 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 774 MPWMB2 In such conditions, the minimum output pulse width that can be obtained is given by: ² MCPSM MPWMSM Minimum_Pulse_Width ------------------------------------------------------------------ - f SYS and the maximum pulse width by: 17-50 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 775 Table 17-25 summarizes the frequency and minimum pulse width values that can be obtained respectively with divide-by-1 and divide-by-256 MPWMSM clock prescaler options, while using a MIOS14 CLOCK frequency of 40 MHz, and for each MCPSM clock divide ratios. MOTOROLA Chapter 17. Modular Input/Output Subsystem (MIOS14) 17-51 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 776 89.6 µs/3584 0.170 0.340 0.681 1.362 2.724 5.449 10.89 21.80 43.59 87.19 174.4 348.8 697.5 1395 2790 5580 96 µs/3840 0.159 0.318 0.636 1.271 2.543 5.086 10.17 20.34 40.69 81.38 162.8 325.5 1302 2604 5208 17-52 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 777 If, however, the long word write coincides with the end of the period, then the transfer of values from the primary to the secondary registers is delayed until the MOTOROLA Chapter 17. Modular Input/Output Subsystem (MIOS14) 17-53 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 778 MPWMSM. Table 17-26. MPWMSM Address Map Address Register MPWMSM0 0x30 6000 MPWMSM0 Period Register (MPWMPERR) See Table 17-27 for bit descriptions. 17-54 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 779 0x30 6028 MPWMSM5 Period Register (MPWMPERR) 0x30 602A MPWMSM5 Pulse Register (MPWMPULR) 0x30 602C MPWMSM5 Count Register (MPWMCNTR) 0x30 602E MPWMSM5 Status/Control Register (MPWMSCR) MPWMSM16 0x30 6080 MPWMSM16 Period Register (MPWMPERR) MOTOROLA Chapter 17. Modular Input/Output Subsystem (MIOS14) 17-55 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 780 0x30 60A6 MPWMSM20 Status/Control Register (MPWMSCR) MPWMSM21 0x30 60A8 MPWMSM21 Period Register (MPWMPERR) 0x30 60AA MPWMSM21 Pulse Register (MPWMPULR) 0x30 60AC MPWMSM21 Count Register (MPWMCNTR) 0x30 60AE MPWMSM21 Status/Control Register (MPWMSCR) 17-56 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 781 The counter register reflects the actual value of the MPWMSM counter. This register is writable only through the period register (PWMPERR). Writes to the counter register will write the same value to the period register. MOTOROLA Chapter 17. Modular Input/Output Subsystem (MIOS14) 17-57...
Page 782 MIOB. 0 MPWMSM not frozen even if the MIOB freeze line is active. 1 MPWMSM frozen if the MIOB freeze line is active. The FREN is cleared by reset. 17-58 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 783 Rising Edge Falling Edge Rising Edge Input INPUT — — — Output Always High — — — — Output Low Pulse Falling Edge Rising Edge Falling Edge MOTOROLA Chapter 17. Modular Input/Output Subsystem (MIOS14) 17-59 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 784 The following sections describe the MPIOSM in detail. A block diagram of one bit of the MPIOSM is shown in Figure 17-29. The MPIOSM contains 16 such blocks. Data Direction Register Data Register Signal Output Driver Input Figure 17-29. MPIOSM 1-Bit Block Diagram 17-60 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 785 As a general practice, it is recommended to write a value in the data register before configuring its corresponding I/O signal as an output. MOTOROLA Chapter 17. Modular Input/Output Subsystem (MIOS14) 17-61 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 786 17.11.8 MPIOSM Register Organization 0x30 6100 MPIOSM Data Register (MPIOSMDR) 0x30 6102 MPIOSM Data Direction Register (MPIOSMDDR) 0x30 6104 Reserved 0x30 6106 Reserved Figure 17-30. MPIOSM — Register Organization 17-62 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 787 For a more detailed description of exception processing in the relevant microprocessors, please refer Chapter 3, “Central Processing Unit” and to the RCPU Reference Manual (RCPURM/AD) MOTOROLA Chapter 17. Modular Input/Output Subsystem (MIOS14) 17-63 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 788 Figure 17-33. MIOS14 Interrupt Structure 17.12.2 MIOS14 Interrupt Request Submodule (MIRSM) Each submodule that is capable of generating an interrupt can assert a flag line when an event occurs. On MPC533 each MIRSM serves 14 submodules. 17-64 MPC533 Reference Manual MOTOROLA...
Page 789 The status register makes flag polling easy, since up to 16 flag bits are contained in one register. MOTOROLA Chapter 17. Modular Input/Output Subsystem (MIOS14) 17-65 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 790 This register contains the interrupt enable bits for the submodules. Each bit corresponds to a given submodule. Field EN15 EN14 EN13 EN12 EN11 — SRESET 0000_0000_0000_0000 Addr 0x30 6C04 Figure 17-35. Interrupt Enable Register (MIOS14ER0) 17-66 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 791 17.12.4.1 Interrupt Status Register (MIOS14SR1) This register contains the flag bits that are raised when the submodules generate an interrupt. Each bit corresponds to a given submodule. MOTOROLA Chapter 17. Modular Input/Output Subsystem (MIOS14) 17-67 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 792 This register is a read only register that contains the interrupt pending bits for the submodules. Each bit corresponds to a given submodule. When one of these bits is set, it means that a submodule raised its flag and the corresponding enable was set. 17-68 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 793 The software may use a find-first-one type of instruction to determine, in the concerned MIRSM, which of the bits is set. The CPU can then serve the requested interrupt. MOTOROLA Chapter 17. Modular Input/Output Subsystem (MIOS14) 17-69...
Page 794 This register contains the interrupt level that applies to the submodules number 15 to zero. Field — — SRESET 0000_0000_0000_0000 Addr 0x30 6C70 Figure 17-41. MIOS14 Interrupt Level Register 1 (MIOS14LVL1) 17-70 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 795 When software attention is not needed for every pulse, the interrupt can be disabled. The software MOTOROLA Chapter 17. Modular Input/Output Subsystem (MIOS14) 17-71...
Page 796 B2 at all times. An interrupt is available for the cases where the software needs to be aware of each new sample. Note that a software option is provided to also generate an interrupt after the first edge. 17-72 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 797 After the trailing edge, the MDASM stops to await further commands from the software. Note that a single edge output can be generated by writing to only one register. MOTOROLA Chapter 17. Modular Input/Output Subsystem (MIOS14) 17-73...
Page 798 The software selects the period of the output signal by programming the MMCSM with a modulus value. The 17-74 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 799 Counting the number of pulses on an input signal is another capability of the MIOS14. Pulse accumulation uses an MMCSM. Since the counters in the counter submodules are software accessible, pulse accumulation does not require the use of an action submodule. MOTOROLA Chapter 17. Modular Input/Output Subsystem (MIOS14) 17-75...
Page 800 16-bit counter. When an MMCSM is used, an interrupt can instead be created when the pulse accumulation reaches a preprogrammed value. To do that, the two’s complement of the value is put in the modulus register and the interrupt occurs when the counter overflows. 17-76 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 801 PPM to act as a parallel-to-serial communications module. Using the PPM in this way can reduce the number of signals required to connect the MPC533 to an external device or devices. The second function allows the PPM to short internal signals thus giving increased access to multiple functions multiplexed on the same device signal.
Page 802 RX Input Configuration RX_CONFIG_2 0x30 5C10 RX Input Configuration — Reserved 0x30 5C12 — — Reserved 0x30 5C14 — RX_DATA 0x30 5C16 Receives data from RX_SHIFTER on SAMP[0:2] update rate 18-2 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 803 In order to reduce the number of signals on the devices, many signals have multiple functions and each signal must be configured for access to any of these functions. The PPM module is designed to increase the availability of MPC533 signal multiplexed functions. It can do this is two ways: •...
Page 804 Figure 18-2. Block Diagram of PPM Module 18.3.1.1 Internal Multiplexing In the MPC533 devices, the PPM module supports multiplexing of two modules: MIOS and GPIO registers, internal to the PPM. Internal multiplexers route data between the MCU internal modules and the external device through the PPM. Four configuration registers, TX_CONFIG_1 and TX_CONFIG_2, RX_CONFIG_1 and RX_CONFIG_2, control these internal multiplexers.
Page 805 TSYNC clock cycle defines a single 16-bit word transmit/receive cycle. The PPM can be configured to transfer data in one of two clock modes, SPI and TDM. Figure 18-5 shows examples of PPM_TCLK in SPI and TDM modes. The frequency of MOTOROLA Chapter 18. Peripheral Pin Multiplexing (PPM) Module 18-5...
Page 806 /2*N) where N is the value in SCALE_TCLK_REG TCLK SYSCLK (see Section 18.4.12, “Scale Transmit Clock Register (SCALE_TCLK_REG) ”) Shading of PPM_RX signifies value is unknown Figure 18-5. PPM Clocks and Serial Data Signals 18-6 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 807 CH[0] PPM_TX CH[0] CH[1] CH[K] CH[0] CH[3] PPM_RX CH[2] Shading of PPM_RX signifies value is unknown Figure 18-6. One Transmit and Receive Cycle in SPI Mode MOTOROLA Chapter 18. Peripheral Pin Multiplexing (PPM) Module 18-7 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 808 OP_16_8 bit setting. For example if the PPM is transferring data on an 8-clock cycle, then setting the sample rate to every 16 clocks will result in lost data. 18-8 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 809 See Table 18-7 for information on these bit descriptions. 18.3.2.2 ETRIG[1] and ETRIG[2] The QAC64E module on the MPC533 has an external trigger input signal that can be used to trigger analog to digital conversions. Using the PPM, these external trigger inputs can be sourced internally.
Page 810 2. Disable both PPMPCR[ENTX] and PPMPCR[ENRX] 3. Wait until PPMPCR[STR] is cleared by the PPM module. This will be done when the next data frame has been sent or received. 4. Set PPMMCR[STOP] 18-10 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 811 Clock Invert. This bit defines the polarity of TCLK clock in both SPI and TDM modes. 0 = Normal clock polarity – active high clocks selected 1 = Inverted clock – active low clocks selected MOTOROLA Chapter 18. Peripheral Pin Multiplexing (PPM) Module 18-11...
Page 812 PPM. See Figure 18-11. To transmit the first data frame correctly, set ENTX and ENRX simultaneously. Table 18-4. SAMP[0:2] Bit Settings SAMP[0:2] Sample Rate Every TCLK Every 2 TCLK Every 4 TCLK Every 8 TCLK 100 – 111 Every 16 TCLK 18-12 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 813 PPM_TCLK One Cycle PPM_TSYNC CH[K] CH[2] CH[3] “1” PPM_TX CH[0] “1” CH[K] CH[0] CH[0] CH[3] PPM_RX CH[2] CH[1] Figure 18-11. Set ENTX while ENRX = 1 MOTOROLA Chapter 18. Peripheral Pin Multiplexing (PPM) Module 18-13 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 814 Each of the 16 fields controls a multiplexer that selects a 1-bit channel from an internal module to the PPM transmit data register. See Table 18-6 for more information on channel control and setting the channel values. 18-14 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 815 (PPMPCR[ENRX] = 0). While receive mode is enabled these registers read as 0x00 and writing them will return TEA (bus error access). Field Reset 0000_0000_0000_0000 Addr 0x30 5C0E Figure 18-16. Receive Configuration Register 1 (RX_CONFIG_1) MOTOROLA Chapter 18. Peripheral Pin Multiplexing (PPM) Module 18-15 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 816 Receive Data Register (RX_DATA) The RX_DATA register receives data from the RX_SHIFTER register. It is updated from RX_SHIFTER at the end of a receive cycle (i.e., rising edge of TSYNC). 18-16 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 817 The RX_SHIFTER register receives data serially from the PPM input signals PPM_RX[0:1] (depending on the value of PPMPCR[OP_16_8]). Data bits are shifted in on every TCLK cycle. Data in the RX_SHIFTER register is delivered directly to the MPC533 internal modules with no wait time.
Page 818 Figure 18-22. General Purpose Data In Register (GPDI) 18.4.10 Short Register (SHORT_REG The SHORT_REG allows the shorting of certain internal signals in the MPC533 devices. This feature allows functions, whose internal signals are multiplexed on external signals, to be accessible simultaneously.
Page 819 If SHORT_CH[x] = 1, transmit TX_DATA[x] during TX_DATA[x] bit time and repeat TX_DATA[x] during TX_DATA[x-1] bit time. Field RESERVED SHORT_CH[7:0] Reset 0000_0000_0000_0000 Addr 0x30 5C28 Figure 18-24. Short Channels Register (SHORT_CH_REG) MOTOROLA Chapter 18. Peripheral Pin Multiplexing (PPM) Module 18-19 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 820 Underlines show bits to be re-transmitted Data transmitted 0x3034 0b 0011 0000 0011 0100 Example 3 SHORT_CH_REG 0x00FF SHORT_CH[7:0] = 1, therefore bits (TX_DATA[1, 3, 5, 7, 9, 11, 13, 15] are enabled for re-transmission. 18-20 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 821 • SCT[6:0] = 1 to 127 F / (2 * SCT[6:0]) SYSCLK Writing to the SCT[6:0] bit field while the PPM is enabled will cause an irregular PPM cycle to occur. MOTOROLA Chapter 18. Peripheral Pin Multiplexing (PPM) Module 18-21 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 822 PPM Registers 18-22 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 823 (MCU) applications targeted for high-speed read performance and high-density byte count requirements. MPC533 The UC3F array uses a single transistor Flash bit cell and is configured for a module of 512 Kbytes (524,288 bytes) of non-volatile memory (NVM). UC3F module is divided into eight 64-Kbyte (65,536-byte) array blocks.
Page 824 — Array block assignment of data or instruction/data space • Internal 64-bit data path architecture • Page mode read — Retains two independent read page buffers — Read page size of 32 bytes (8 words). 19-2 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 825 UC3F 5-V power supply VFLASH provides a 5-V supply to the UC3F module which is used for read, program, and erase operations. VFLASH must be in the range of 4.75 V to 5.25 V (5 V ± 5%) during operation. MOTOROLA Chapter 19. CDR3 Flash (UC3F) EEPROM 19-3...
Page 826 The UC3F module control registers, shown in Table 19-2, are selected with individual register selects generated from the BIU. As such, each Flash module that is designed using the UC3F EEPROM module may uniquely define the addressing of the control register block. 19-4 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 827 Operations to the UC3F array should be delayed for at least 1µs after clearing the STOP bit. 0 = UC3F array is enabled 1 = UC3F array is disabled (low-power mode) MOTOROLA Chapter 19. CDR3 Flash (UC3F) EEPROM 19-5 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 828 ACCESS can be read whenever the registers are enabled. ACCESS provides a method to bypass the UC3F EEPROM module censorship. 0 Censored - UC3F array access allowed only if the censorship state is no censorship 1 Allows all UC3F array access 19-6 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 829 DATA bit. 0 array block m is placed in both data and instruction address spaces 1 array block m is placed in data address space MOTOROLA Chapter 19. CDR3 Flash (UC3F) EEPROM 19-7 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 830 0 array block m is unprotected 1 array block m is protected Note that the LOCK bit is in a different bit location on the MPC533 than in the MPC555. It was at bit 0 of CMFMCR. 19.2.1.3 UC3F EEPROM Extended Configuration Register...
Page 831 SBDATA bit is compared with the address space attributes to determine validity of an array access. 0 small block M is placed in both Data and Instruction address spaces 1 small block M is placed in Data address space MOTOROLA Chapter 19. CDR3 Flash (UC3F) EEPROM 19-9 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 832 11 small blocks are part of the lowest and highest numbered blocks of the UC3F array 23:31 FLASHID Flash module identification code. The FLASHID value is assigned by Motorola and used internally for tracking purposes. The FLASHID field is read only and writes have no effect. 19-10...
Page 833 PEGOOD is reset when either EHV is asserted or SES is cleared. See Figure 19-4 for a timing diagram of when PEGOOD is valid. 0 program or erase operation failed 1 program or erase operation was successful MOTOROLA Chapter 19. CDR3 Flash (UC3F) EEPROM 19-11 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 834 0 Array block M is not selected for program or erase 1 Array block M is selected for program or erase — Reserved 19-12 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 835 STOP, PROTECT, SBPROTECT, BLOCK, SBBLOCK, CSC, SBEN, and PE bits. 0 UC3F EEPROM not configured for program or erase operation 1 Configure UC3F EEPROM for program or erase operation MOTOROLA Chapter 19. CDR3 Flash (UC3F) EEPROM 19-13 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 836 32 bytes of data are transferred from the array core. Only the addressed 64 bits of data will be transferred to the BIU. This type of array read access is an off-page read. The BIU 19-14 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 837 SBEN[0] = 0 in this array configuration, the shadow row is treated as part of the host block. The corresponding PROTECT and BLOCK bits are used to control program and erase operation of the shadow row. NOTE A module cannot read its own shadow row. MPC533 0x00 Reset Configuration Word 0x03...
Page 838 CLKOUT drive strength to be full. See Table 6-7 for more information. BDRV controls the default state of COM[1] in the SIUMCR. 0 Full drive 1 Reduced drive 19-16 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 839 Peripheral mode enable — This bit determines if the chip is in peripheral mode. A detailed description is in Table 6-13 The default value is no peripheral mode enabled. 17:18 Single chip select — This field defines the mode of the MPC533. 00 Extended chip, 32 bits data 01 Extended chip, 16 bits data...
Page 840 19.2.4 UC3F EEPROM 512-Kbyte Array Configuration Figure 19-7, the array configuration diagram, shows the UC3F configuration for the MPC533 512-Kbyte arrays. The shaded blocks in Figure 19-7 indicate the location of the shadow row. Figure 19-7. 512-Kbyte Array Configuration 19.3 UC3F Operation The following sections describe the operation of the UC3F EEPROM during various operational modes.
Page 841 32 bytes of information is fetched from the UC3F array, and the addressed data is driven onto the data bus. A data fetch from the UC3F array is an off-page read operation. MOTOROLA Chapter 19. CDR3 Flash (UC3F) EEPROM 19-19...
Page 842 32 bytes of data from the Flash array and transfers the addressed data to the data bus. In the MPC533, UC3F module contains two 32-byte read page buffers. In module, one buffer is dedicated to the most recently accessed instruction fetches and the other read page buffer is dedicated to the most recently loaded data access.
Page 843 19.3.7.1 Program Sequence The UC3F EEPROM module requires a sequence of writes to the high voltage control register (UC3FCTL) and to the program data latch in order to enable the high voltage to the MOTOROLA Chapter 19. CDR3 Flash (UC3F) EEPROM 19-21...
Page 844 B0EPEE inputs are setup prior to the assertion of EHV. 5. Read the UC3FCTL register until HVS = 0. 6. Read the UC3FCTL, confirm PEGOOD = 1. 7. Write EHV = 0. 19-22 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 845 State Mode Transition Requirement State Normal Operation: Write PE = 0, SES = 1. Normal array reads and register accesses. The block protect information can be modified. MOTOROLA Chapter 19. CDR3 Flash (UC3F) EEPROM 19-23 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 846 SIE must be set to a 1 prior to initiating the programming sequence. Only the lowermost addresses are used to encode words that get programmed in the shadow row. The 19-24 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 847 0 or small block 0 if SBEN[0] = 1. The embedded program/erase algorithm first pre-programs all bits in blocks selected for erase prior to actually erasing the selected blocks. MOTOROLA Chapter 19. CDR3 Flash (UC3F) EEPROM 19-25...
Page 848 EHV to determine the array protection state for the erase operation. It is assumed that the EPEE and B0EPEE inputs are setup prior to the assertion of EHV. 5. Read the UC3FCTL register until HVS = 0. 19-26 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 849 Write SES = 0 or a reset. Accesses to the registers are normal register Write EHV = 1. accesses. A write to UC3FCTL can change SES or EHV. MOTOROLA Chapter 19. CDR3 Flash (UC3F) EEPROM 19-27 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 850 Reads to the array block or blocks targeted for erase return indeterminate data since only a partial erase operation has been performed. The erase operation may be resumed by setting HSUS = 0. 19-28 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 851 UC3FCTL register is asserted (HSUS = 1) to suspend the current program or erase operation. When the UC3F module is re-enabled, the suspended program or erase operation may be resumed by writing the HSUS bit to a 0. MOTOROLA Chapter 19. CDR3 Flash (UC3F) EEPROM 19-29...
Page 852 Information censorship, No UC3F array accesses allowed. 01 or 10 No censorship, UC3F array accesses allowed. Cleared censorship, No UC3F array accesses allowed. Emulated censorship, No UC3F array accesses allowed. No censorship, UC3F array accesses allowed. 19-30 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 853 CENSOR[0:1] can be put into the no censorship state. While clearing CENSOR[0:1] the entire UC3F array is erased. Thus the information stored in the UC3F array is made invalid while clearing CENSOR[0:1]. MOTOROLA Chapter 19. CDR3 Flash (UC3F) EEPROM 19-31...
Page 854 EEPROM status states #3, #4 and #5 from Table 21-10. The erase interlock write is only valid if all blocks of the array are selected for erase and not protected. BLOCK[0:7] and SBBLOCK[0:1] set to 1, as well as 19-32 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 855 There are three states of censorship that CENSOR[0:1] can select. These are—cleared censorship, no censorship (two states) and information censorship. These three states, state values, transitions, and state of censorship are shown in Figure 19-10. MOTOROLA Chapter 19. CDR3 Flash (UC3F) EEPROM 19-33...
Page 856 19.3.12 Background Debug Mode or Freeze Operation While in background debug mode, the UC3F should respond normally to accesses except that LOCK is writable. See the LOCK bit in Table 19-3. 19-34 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 857 Chapter 20 CALRAM Operation The calibration static random access memory (CALRAM) module provides the MPC533 with a general purpose memory that may be read from or written to as either bytes, half-words, or words. In addition to this, a portion of the CALRAM, called the overlay region, can be used for calibration.
Page 858 4-Kbyte Overlay Figure 20-1. System Block Diagram 20.3 CALRAM Memory Map The MPC533 chip internal memory map is shown in Figure 20-2. The CALRAM module is divided into two sections. • Control section: — Includes all the registers in the CALRAM module •...
Page 859 CALRAM (32 Kbytes) 0x3F FFFF Figure 20-2. MPC533 Memory Map with CALRAM Address Ranges When the normal device power (VDD) is off, portions of the CALRAM array can be powered by separate power supply sources () as shown in Figure 20-3, thus allowing the data to be retained.
Page 860 RAM 4K A3 0x3F E000 RAM 4K A2 0x3F F000 IRAMSTBY (Overlay portion of RAM 4K A1 Standby RAM) 0x3F FFFF Figure 20-3. Standby Power Supply Configuration for CALRAM Array 20-4 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 861 L-bus from the array or the register, instead it drives 0’s. Also, aborted accesses maintain data integrity. Aborted writes do not corrupt data in register/array, and aborted reads do not drive the requested data on L-bus. MOTOROLA Chapter 20. CALRAM Operation 20-5...
Page 862 512 bytes as shown in Figure 22-5. As described in section Section 20.5.2, “CALRAM Region Base 20-6 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 863 Figure 22-7 illustrates the address spaces occupied by the two CALRAM modules available in MPC533. If the CLPS bit in OVLCR register is set, then each of the eight region sizes is forced to be 4 bytes long as shown in Figure 21-7,regardless of the value programmed in the RGN_SIZE field.
Page 864 When the address matches to more than one enabled portion of the overlay region, the effective region is the region with the highest priority. Priority is determined by the region number; the highest priority assigned to the lowest region number. 20-8 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 865 CALRAM registers requires the bus master to be in supervisor data mode. On a privilege violation, the register is not accessed and the access generates an error. Table 22-4 shows the register address map for the MPC533. Any unimplemented bits in CALRAM registers return 0’s on a read and writes to these bits are ignored.
Page 866 This mode provides power savings by using the first cycle to decode any L-bus access for an address match to where the array resides. 0 CALRAM module in one-cycle operation 1 CALRAM module in two-cycle operation 3:19 — Reserved 20-10 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 867 Same as R0 except for address ranges shown on Table 20-2. Same as D0 except for address ranges shown on Table 20-2. Same as S0 except for address ranges shown on Table 20-2. MOTOROLA Chapter 20. CALRAM Operation 20-11 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 868 CRAM_RBA0, which provides the base address of overlay region 0. Field RGN_SIZE — SRESET Unaffected 0000_000 Unaffected Field — SRESET Unaffected Addr 0x38 0008–0x38 0024 Figure 20-7. CALRAM Region Base Address Register (CRAM_RBAx) 20-12 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 869 Note: The overlay size of 8 bytes cannot be selected 20.5.3 CALRAM Overlay Configuration Register (CRAM_OVLCR) Field OVL DERR CLPS — SRESET 0000_0000_0000_0000 Field — SRESET 0000_0000_0000_0000 Addr 0x38 0028 Figure 20-8. CALRAM Overlay Configuration Register (CRAM_OVLCR) MOTOROLA Chapter 20. CALRAM Operation 20-13 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 870 CRAM_OTR is also defined as READI_OTR. See Section 22.1.1.1, “User-Mapped Register (OTR).” Field Ownership Trace Register SRESET 0000_0000_0000_0000 Field Ownership Trace Register SRESET 0000_0000_0000_0000 Addr 0x38 002C Figure 20-9. CALRAM Ownership Trace Register (CRAM_OTR) 20-14 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 871 The program instructions flow is visible on the external bus when the MPC533 is programmed to operate in serial mode and show all fetch cycles on the external bus. This mode is selected by programming the ISCT_SER (instruction fetch show cycle control) field in the I-bus support control register (ICTRL), as shown in Table 22-28.
Page 872 These cycles can generate regular bus cycles (address phase and data phase) when the instructions reside only in one of the 21-2 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 873 The sequential instructions listed here affect the machine in a manner similar to indirect branch instructions. Refer to Section 21.1.3, “Sequential Instructions Marked as Indirect Branch.” Table 21-2 shows VF[0:2] encodings for instruction queue flush information. MOTOROLA Chapter 21. Development Support 21-3...
Page 874 When the CPU is in debug mode, the VF pins equal ‘000’ and the VFLS pins equal ‘11’. For more information on debug mode refer to Section 21.3, “Development System Interface.” 21-4 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 875 • Window trace — Window trace is useful when a record of the program trace between two events is needed. In case window trace is needed the VSYNC pin MOTOROLA Chapter 21. Development Support 21-5...
Page 876 12. Return to the regular code run (issue an rfi). The first report on the VF pins is a VSYNC (VF = 011) 13. The external hardware stops sampling the program trace information upon the report on the VF pins of VSYNC 21-6 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 877 VSYNC on the VF pins (VF = 011) until all addresses marked with the program trace cycle attribute were visible externally. Therefore, the external hardware should stop sampling the value of the status pins (VF and MOTOROLA Chapter 21. Development Support 21-7...
Page 878 Branch trace messaging for the RCPU is accomplished by snooping the U-bus address, data and program trace signals, and RCPU VF and VFLS signals, and performing algorithms necessary to generate the trace messages. 21-8 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 879 — If the decoded branch instruction is conditional and predicted taken, instructions subsequent to the branch instruction in the prefetch queue are flushed. Fetching of instructions is started from the new target address. MOTOROLA Chapter 21. Development Support 21-9 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 880 3. Taken branches may be cancelled due to misprediction or exceptions. 4. Executed instructions (sequential or branches) which are subsequent to the exception-causing instruction will be flushed from the history buffer due to exception. 21-10 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 881 Branch (direct or indirect) NOT taken (misprediction) The RCPU VF signals indicate (instruction pre-fetch) queue flush information in the clock following a taken change-of-flow indication. This encoding is as follows. MOTOROLA Chapter 21. Development Support 21-11 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 882 21.2 Watchpoints and Breakpoints Support Watchpoints, when detected, are reported to the external world on dedicated pins but do not change the timing and the flow of the machine. Breakpoints, when detected, force the 21-12 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 883 External breakpoints can be generated by any of the peripherals of the system, including those found on the MPC533 or externally, and also by an external development system. Peripherals found on the external bus use the serial interface of the development port to assert the external breakpoint.
Page 884 Types”). Using the AND-OR logic structures “in range” and “out of range” detections (on address and on data) are supported. Using the counters, it is possible to program a breakpoint to be recognized after an event was detected a predefined number of times. 21-14 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 885 Refer to Section 21.2.1.2, “Byte and Half-Word Working Modes.” MOTOROLA Chapter 21. Development Support 21-15 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 886 • Instructions with load/store breakpoints are executed. The machine branches to the breakpoint exception routine AFTER it executes the instruction. The address of the access is placed in the BAR (breakpoint address register). 21-16 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 887 MOTOROLA Chapter 21. Development Support 21-17 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 888 One L-data comparator = 0x4e204e20 and program for greater than One L-data comparator = 0x9c409c40 and program for less than Both byte masks = 0x0 Both L-data comparators program to half-word mode — Result: 21-18 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 889 When the CPU is programmed to recognize internal breakpoints only when MSRRI = 1, it is possible to debug all parts of the code except when the machine status save/restore registers (SRR0 and SRR1), DAR (data address register) and DSISR (data storage interrupt MOTOROLA Chapter 21. Development Support 21-19...
Page 890 This method does not work for the following boundary cases: • Less than or equal of the largest unsigned number (1111...1) • Greater than or equal of the smallest unsigned number (0000...0) 21-20 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 891 Comparators (A&B) IWP1 Second instruction watchpoint Comparator B Comparator (A | B) IWP2 Third instruction watchpoint Comparator C Comparators (C&D) IWP3 Fourth instruction watchpoint Comparator D Comparator (C | D) MOTOROLA Chapter 21. Development Support 21-21 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 892 Each byte comparator has a mask bit and generates two output signals: equal and less than, if the mask bit is not set. Therefore, each 32 bit comparator has eight output signals. 21-22 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 893 Comparator G Load/store IWP3, Comparator F Comparator H watchpoint ignore instruction Comparators (E&F) Comparators (G&H) events Comparators (E | F) Comparators (G | H) ignore I-addr events ignore L-data events MOTOROLA Chapter 21. Development Support 21-23 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 894 Size Compare Size Logic Logic Byte Mask Byte 0 Byte 1Byte 2 Byte 3 Byte 0 Byte 1 Byte 2 Byte 3 Byte Mask Figure 21-5. Load/Store Support General Structure 21-24 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 895 ICTRL and the LCTRL2 using mfspr. For the exact bits placement refer to Section 21.6.10, “L-Bus Support Control Register 2” and to Section 21.6.10, “L-Bus Support Control Register 2.” MOTOROLA Chapter 21. Development Support 21-25 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 896 When in debug mode an rfi instruction will return the machine to its regular work mode. The relationship between the debug mode logic to the rest of the CPU chip is shown in Figure 21-6. 21-26 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 897 DSDO Shift Register DSDI Figure 21-6. Functional Diagram of MPC533 Debug Mode Support The development port provides a full duplex serial interface for communications between the internal development support logic of the CPU and an external development tool. The development port can operate in two working modes: the trap enable mode and the debug mode.
Page 898 Figure 21-7 illustrates the debug mode logic implemented in the CPU. 21-28 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 899 21.3.1.1 Debug Mode Enable vs. Debug Mode Disable For protection purposes two possible working modes are defined: debug mode enable and debug mode disable. These working modes are selected only during reset. MOTOROLA Chapter 21. Development Support 21-29 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 900 Because SRESET negation is done by an external pull up resistor any reference here to SRESET negation time refers to the time the MPC533 releases SRESET. If the actual negation is slow due to a large resistor, set up time for the debug port signals should be set accordingly.
Page 901 • Implementation specific instruction protection error • Implementation specific data protection error • External interrupt, recognized when MSREE = 1 • Alignment interrupt • Program interrupt • Floating point unavailable exception MOTOROLA Chapter 21. Development Support 21-31 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 902 = 0) and a machine check interrupt is detected. However, if a machine check interrupt is detected when MSR[ME] = 0, debug mode is enabled and the check stop enable bit in the 21-32 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 903 (ecr_or) is asserted for one clock cycle to report to the development port that an exception occurred and execution continues in debug mode without any change in SRR0 and SRR1. ECR_OR MOTOROLA Chapter 21. Development Support 21-33...
Page 904 The development system may monitor the freeze status to make sure the MPC533 is out of debug mode. It is the responsibility of the software to read the exception cause register (ECR) before performing the rfi.
Page 905 DSCK or CLKOUT depending on the clock mode. Data will be valid a setup time before the rising edge of the clock and will remain valid a hold time after the rising edge of the clock. MOTOROLA Chapter 21. Development Support 21-35...
Page 906 The freeze indication means that the processor is in debug mode (i.e., normal processor execution of user code is frozen). On the MPC533, the freeze state can be indicated by three different pins. The FRZ signal is generated synchronously with the system clock. This indication may be used to halt any off-chip device while in debug mode as well as a handshake means between the debug tool and the debug port.
Page 907 If what the CPU is expecting and what the register receives from the serial port do not match (instruction instead of data) the mismatch is used to signal a sequence error to the external development tool. MOTOROLA Chapter 21. Development Support 21-37...
Page 908 The first method allows the transmission to occur without being externally synchronized with CLKOUT, in this mode a serial clock DSCK must be supplied to the MPC533. The other communication method requires a data to be externally synchronized with CLKOUT.
Page 909 7 or 32 input data bits. Debug Port drives “ready” bit onto DSDO when CPU starts a read of DPIR or DPDR. Figure 21-10. Synchronous Self Clock Serial Communication MOTOROLA Chapter 21. Development Support 21-39...
Page 910 The encoding of data shifted into the development port shift register (through the DSDI pin) is shown in Table 21-13 and Table 21-14 below: 21-40 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 911 In trap enable mode the only response out of the development port is “sequencing error.” Data that can come out of the development port is shown in Table 21-15. “Valid data from CPU” and “CPU interrupt” status cannot occur in trap enable mode. MOTOROLA Chapter 21. Development Support 21-41...
Page 912 CPU are transmitted with the mode bit cleared indicating a 32-bit data field. The encoding of data shifted into the development port shift register (through the DSDI pin) is shown below in Table 21-16. 21-42 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 913 This is the result of an instruction to move the contents of a general purpose register to the debug port data register (DPDR). The valid data encoding has the highest priority of all status outputs and will be reported even if an interrupt occurs MOTOROLA Chapter 21. Development Support 21-43...
Page 914 This procedure can be accomplished by repeating the following sequence of transactions from the development tool to the debug port for the number of data words to be down loaded: 21-44 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 915 “end download procedure” command is issued to the debug port. Note that, the internal general purpose register 31 is used for temporary storage data value. Before beginning the “fast download procedure” by the “start download procedure MOTOROLA Chapter 21. Development Support 21-45...
Page 916 Section 21.6.2, “Comparator A–D Value Registers (CMPA–CMPD)” through Section 21.6.13, “Development Port Data Register (DPDR),” follow the same SPR order. The registers are accessed with the mtspr and mfspr instructions. 21-46 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 917 See Section 21.6.13, “Development Port Data Register (DPDR)” for bit descriptions. 21.6.1 Register Protection Table 21-18 and Table 21-19 summarize protection features of development support registers during read and write accesses, respectively. MOTOROLA Chapter 21. Development Support 21-47 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 918 Write is not performed. Program exception is generated. 21.6.2 Comparator A–D Value Registers (CMPA–CMPD) Field CMPA-D Reset Unaffected Field CMPAD Reset Unaffected Addr SPR144–SPR147 Figure 21-15. Comparator A–D Value Register (CMPA–CMPD) 21-48 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 919 Program exception bit. Set when the program exception is asserted. FPUVE Floating point unavailable exception bit. Set when the program exception is asserted. DECE Decrementer exception bit. Set when the decrementer exception is asserted. MOTOROLA Chapter 21. Development Support 21-49 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 920 21.6.4 Debug Enable Register (DER) This register enables selectively masking the events that may cause the processor to enter into debug mode. 21-50 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 921 0 Debug mode entry disabled (reset value) 1 Debug mode entry enabled 11:12 — Reserved SYSEE System call exception enable bit 0 Debug mode entry disabled (reset value) 1 Debug mode entry enabled MOTOROLA Chapter 21. Development Support 21-51 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 922 0 Debug mode entry disabled 1 Debug mode entry enabled (reset value) DPIE Development port interrupt enable bit 0 Debug mode entry disabled 1 Debug mode entry enabled (reset value) 21-52 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 923 Breakpoint Counter B Value and Control Register Field CNTV Reset Unaffected Field — CNTC Reset 0000_0000_0000_0000 Addr SPR 151 Figure 21-19. Breakpoint Counter B Value and Control Register (COUNTB) MOTOROLA Chapter 21. Development Support 21-53 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 924 SPR 154, SPR 155 Figure 21-21. Comparator G–H Value Registers (CMPG–CMPH) Table 21-26. CMPG-CMPH Bit Descriptions Bits Mnemonic Description 0:31 CMPG-H Data bits to be compared Note: These registers are unaffected by reset. 21-54 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 925 0001 the last byte of the word is masked 26:29 CHBMSK Byte mask for 2nd L-data comparator 1111 all bytes are masked 30:31 — Reserved — Note: LCTRL1 is cleared following reset. MOTOROLA Chapter 21. Development Support 21-55 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 926 0 Don’t care 1 Care LW0LD 1st L-bus watchpoint L-data events selection 00match from comparator G 01match from comparator H 10match from comparators (G&H) 11match from comparators (G | H) 21-56 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 927 1 non-masked mode; breakpoints are always recognized 21:27 — Reserved DLW0EN Development port trap enable selection of the 1st L-bus watchpoint (read only bit) 0 trap disabled (reset value) 1 trap enabled MOTOROLA Chapter 21. Development Support 21-57 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 928 If the processor aborts a fetch of the target of a direct branch (due to an exception), the target is not always visible on the external pins. Program trace is not affected by this phenomenon. 21-58 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 929 (read only bit) DIWP2EN Development port trap enable selection of the 3rd I-bus watchpoint (read only bit) DIWP3EN Development port trap enable selection of the 4th I-bus watchpoint (read only bit) MOTOROLA Chapter 21. Development Support 21-59 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 930 RCPU is not serialized (normal mode) and show cycles will be performed for all indirect changes in the program flow RCPU is not serialized (normal mode) and no show cycles will be performed for fetched instructions 21-60 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 931 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Lsb Field Data Reset Unaffected Addr SPR 630 Figure 21-26. Development Port Data Register (DPDR) MOTOROLA Chapter 21. Development Support 21-61 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 932 Development Support Registers 21-62 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 933 (selected) internal memory resources. Data trace also allows for calibration variable acquisition in automotive powertrain development systems. MOTOROLA Chapter 22. READI Module 22-1 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 934 28 MHz, this translates to a download rate of 28 Mbits/s. — Eight bits are uploaded per clock in full port mode. — Two bits are uploaded per clock in reduced port mode. 22-2 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 935 Security USIU Figure 22-1. READI Functional Block Diagram 22.0.3 Modes of Operation The various operating modes of the READI module are: 1. Reset 2. Secure 3. Normal 4. Disabled MOTOROLA Chapter 22. READI Module 22-3 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 936 The queue is only 16 messages deep on revisions prior to . For reduced port mode, the data trace feature should not be used, or used sparingly, so as not to cause queue overruns. 22-4 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 937 Data Trace — Data Write Message. Refer to Section 22.4.2.1, “Data Write Message.” Data Trace — Data Read Message. Refer to Section 22.4.2.2, “Data Read Message.” Error Message. Refer to Table 22-20. MOTOROLA Chapter 22. READI Module 22-5 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 938 Program Trace — Direct Branch Synchronization Message With Compressed Code. Available in only. 61 (0x3D) Program Trace — Indirect Branch Synchronization Message With Compressed Code. Available in only. Vendor-defined messages outlined in Table 22-2 are also supported by READI. 22-6 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 939 Public Messages Messages on the auxiliary signals for accomplishing common visibility and controllability requirements e.g. DRM and DWM. RCPU Processor that implements the PowerPC-based architecture used in the Motorola MPC500 family of microcontrollers. READI Real time Embedded Applications Development Interface.
Page 940 Their functions are explained below. The current task/process (CTP) field is updated by the operating system software to provide task/process ID information. The OTR register can only be accessed by supervisor data 22-8 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 941 Data Trace Attributes Register 1 (DTA1) Read/Write 21 (0x15) Data Trace Attributes Register 2 (DTA2) Read/Write Not available on all revisions. Refer to the device errata for the version of silicon in use. MOTOROLA Chapter 22. READI Module 22-9 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 942 READI Manufacturer Design Center. This field identifies the manufacturer’s design center. The MPC533 has a value of 0x02. 10:19 21:12 READI Part Number. This part number identification field. The MPC533 field value is 0x36. 20:30 11:1 READI Manufacturer ID. This field identifies the manufacturer of the device, Motorola’s ID is 0x0E.
Page 943 Debug mode is enabled through READI (RCPU is still in normal mode, out of reset) Debug mode is enabled through READI and entered out-of-reset. Debug mode entry causes RCPU to halt. MOTOROLA Chapter 22. READI Module 22-11 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 944 1 Program trace message contain the I-CNT packet. 22.1.1.6 User Base Address Register (UBA) The UBA register defines the memory map address for the OT register. Table 22-10 gives a description of the register bits. 22-12 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 945 0:31 31:0 The user base address (UBA) field defines the memory map address for the OT register. The MPC533 user base address is 0x38002C. The UBA register is read-only by the development tool. 22.1.1.7 Read/Write Access Register (RWA) The RWA register provides DMA-like access to memory-mapped locations, MPC500 special purpose registers, and READI tool mapped registers.
Page 946 NOTE: The RWD field of the UDI register is shared with the WD field of the RWA register. The read/write (RW) field can be configured to allow selection of a read or a write access. 0 Read access 1 Write access 22-14 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 947 The UDI register, a 34-bit register, is used to store the data to be written for block write access, and the data read for read (single and block) accesses. Table 22-12 gives a description of the register bits. MOTOROLA Chapter 22. READI Module 22-15...
Page 948 Table 22-14. Write Access Status Status Write access has completed and no access error occurred Write access error occurred (Error Message sent out) Write access has not yet completed Not allowed 22-16 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 949 DTEA DTSA RSTI 0000_0000_0000_0000 Field DTSA RSTI 0000_0000_0000_00 Addr 0x14 (DTA1), 0x15 (DTA2) Figure 22-10. READI Data Trace Attributes 1 Register (DTA1) READI Data Trace Attributes 2 Register (DTA2) MOTOROLA Chapter 22. READI Module 22-17 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 950 The control and status information is accessed via the four auxiliary access public messages: device ready for upload/download, upload request (tool requests information), download request (tool provides information), and upload/download information (device/tool provides information). 22-18 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 951 To write control or status data to READI tool mapped registers the following sequence would be required. 1. The tool confirms that the device is ready. The tool transmits the download request message (TCODE 18) which contains write data, and register opcode. MOTOROLA Chapter 22. READI Module 22-19 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 952 To get the best performance from the system, PTM should be set to 1 and ISCTL should be set to 0b10. It is also recommended that the USIU be programmed to ignore instruction 22-20 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 953 The ICTRL register must be programmed such that a show cycle will be performed for all changes in the program flow (ISCTL field = 0b01), or the PTM bit must be set and ISCTL must be set to a value other than 0b11. (See Table 22-21.) MOTOROLA Chapter 22. READI Module 22-21...
Page 954 If background debug mode (BDM) is enabled, the ICTRL register cannot be modified through user program. This register can only be accessed through the development port. Figure 22-11. Enabling Program Trace Out of System Reset 22-22 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 955 Message Clock-In (MCKI) is a input clock from development tools for timing of MDI and MSEI signal functions. MCKI frequency has to be less than or equal to one half of MCKO frequency. MOTOROLA Chapter 22. READI Module 22-23 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 956 Internal latching of MDI will occur MDI[0] on rising edge of MCKI. Two signals are implemented on the MPC533. MDI[1:0] are used in full port mode, MDI[0] only is used in reduced port mode.
Page 957 MSEI/MSEO are used to signal the end of variable-length packets and messages. They are not required to indicate end of fixed length packets. MSEI/MSEO are sampled on the rising edge of MCKI and MCKO respectively. MOTOROLA Chapter 22. READI Module 22-25...
Page 958 Figure 22-13. Auxiliary Signal Packet Structure for Program Trace Indirect Branch Message Figure 22-14 illustrates the state diagram for MSEI/MSEO transfers. In the End Message state, data on MDI/O is ignored. 22-26 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 959 Message Device Fixed Task/Process ID tag Program Trace — Fixed TCODE number = 3 From Direct Branch Device Variable number of sequential instructions executed Message since last taken branch MOTOROLA Chapter 22. READI Module 22-27 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 960 Program Trace — Fixed TCODE number = 12 (0xC) From Indirect Branch Device Variable number of sequential instructions executed Synchronization since last taken branch Message (PTSM = 1) Variable full target address 22-28 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 961 Variable resource code Refer to Table 22-20 for the error message codes. Not available on all revisions. Refer to the device errata for the version of silicon in use. MOTOROLA Chapter 22. READI Module 22-29 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 962 (compressed code) Program Trace — Fixed TCODE number = 60 (0x3C) From Direct Branch Device Fixed Bit address Synchronization Message With Variable Current instruction address Compressed Code (PTSM = 0) 22-30 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 963 For variable length fields, the transmitted size of the field is determined as the bits from the least significant bit to the most significant non-zero valued bit, (i.e., most significant 0 value bits are not transmitted). MOTOROLA Chapter 22. READI Module 22-31 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 964 Variable Variable Variable 64 bits 16 bits Data Write (0xD) Max = 1 Max = 25 Max = 32 Synchronization Min = 1 Min = 1 Min = 8 Message 22-32 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 965 Compressed Code Program Trace — Fixed = 6 Variable 35 bits 13 bits Direct Branch (0x3C) Max = 23 Synchronization Min = 1 Message With Compressed Code (PTSM = 0) MOTOROLA Chapter 22. READI Module 22-33 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 966 Within a field, the lowest significant bits are shifted out first. Figure 22-15 shows the transmission sequence of a message which is made up of a 22-34 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 967 Tx = TCODE number (fixed) Ix = Number of sequential instructions (variable) Ax = Unique portion of the address (variable) NOTE During clock 7, the tool should ignore data on MDO signals. MOTOROLA Chapter 22. READI Module 22-35 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 968 BTMs are in sequence and DTMs are in sequence, however, temporal order of DTMs interleaved with BTMs may not be accurate with regard to logical flow of code. 22-36 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 969 EVTI is sampled at the negation of RSTI. Because EVTI is asserted, the READI module is enabled. Reset configuration information must be valid on EVTI at least 4 system clocks prior to RSTI negation. Figure 22-16. READI Module Enabled MOTOROLA Chapter 22. READI Module 22-37 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 970 If EVTI is negated at negation of RSTI, the READI module will be disabled. No trace output will be provided, and output auxiliary signals will be three-stated. This is illustrated in Figure 22-17. 22-38 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 971 Program trace is implemented via branch trace messaging (BTM) as per the IEEE-ISTO 5001-1999 definition. 22.3.1 Branch Trace Messaging Branch trace messaging facilitates program trace by providing the following types of information: MOTOROLA Chapter 22. READI Module 22-39 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 972 The program trace direct branch message has the following format: [1 - 8 bits] [6 bits] Sequence Count TCODE (3) Max Length = 14 bits Min Length = 7 bits Figure 22-18. Direct Branch Message Format 22-40 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 973 Max Length = 40 bits Min Length = 14 bits Figure 22-20. Indirect Branch Message Format with Compressed Code Bit Pointer Reserved Figure 22-21. Bit Pointer Format with Compressed Code MOTOROLA Chapter 22. READI Module 22-41 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 974 0, after the program trace correction message is sent. Table 22-27. Program Trace Correction Due to a Mispredicted Branch Time Processor State Message sent Sequential Instruction Sequential Instruction Sequential Instruction Sequential Instruction Sequential Instruction 22-42 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 975 (this includes the mispredicted branch instruction which is considered to be a sequential instruction). Table 22-28. Program Trace Correction Due to an Exception Time Processor State Message sent Sequential Instruction Sequential Instruction Sequential Instruction MOTOROLA Chapter 22. READI Module 22-43 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 976 (it was not transmitted out). Note: The sequential instruction at Time 8 did not retire and is included in the correction number. The program trace correction message has the following format: 22-44 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 977 • Upon entering or exiting code compression mode, the next BTM will be a synchronization message. • The next change-of-flow instruction fetch following VSYNC will be a synchronization message. MOTOROLA Chapter 22. READI Module 22-45 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 978 [1 – 23 bits] [1 bit] Full target address TCODE (11) Messages Cancelled Max Length = 30 bits Min Length = 8 bits Figure 22-23. Direct Branch Synchronization Message Format (PTSM = 0) 22-46 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 979 Bit address TCODE (60) Full target address Max Length = 35 bits Min Length = 13 bits Figure 22-27. Direct Branch Synchronization Message Format With Compressed Code (PTSM = 0) MOTOROLA Chapter 22. READI Module 22-47 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 980 When more than 256 instructions have run without a branch being taken a program trace resource full message will be generated that indicates the maximum I-CNT value has been reached. The I-CNT field has a maximum width of 8 bits. 22-48 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 981 (most-significant 0-padded) message address with the previously decoded address gives the current address. Figure 22-32 shows how a relative address is generated and how it can be used to recreate the original address. MOTOROLA Chapter 22. READI Module 22-49 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 982 The error message has the following format: [6 bits] [5 bits] Error Code (0b0 0000, TCODE (8) 0b0 0001, 0b0 0010, 0b0 0111) Length = 11 bits Figure 22-33. Error Message (Queue Overflow) Format 22-50 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 983 3. An exception can cause cancellation of multiple taken branches which may require cancelling multiple program trace messages. MOTOROLA Chapter 22. READI Module 22-51 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 984 00110100 00000101 00000000 TCODE = 4 Number of Sequential Instructions since last taken branch = 4 Don’t care data Relative Address = 0x534 (idle clock) Figure 22-35. Indirect Branch Message 22-52 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 985 Figure 22-37. Program Trace Correction Message MCKO MSEO MDO[7:0] 11001000 00000001 00000000 TCODE = 8 Don’t care data Error Code = 0b00111 (Program/Data/Ownership trace overrun) (idle clock) Figure 22-38. Error Message (Program/Data/Ownership Trace Overrun) MOTOROLA Chapter 22. READI Module 22-53 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 986 10000110 11001010 00000000 TCODE = 60 (0x5C) Don’t care data Bit address = 9 (idle clock) Full target address = 0xCA864 Figure 22-41. Direct Branch Synchronization Message with Compressed Code 22-54 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 987 In early versions of the READI module, 8-bit data cannot be differentiated from 16-bit data when the 8 MSBs are set to zero. See the device mask set errata list for customer information. MOTOROLA Chapter 22. READI Module 22-55 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 988 • Initial data trace message upon exit of any system reset will be a synchronization message. • Upon exit of sleep, deep-sleep and low power down mode, the first data trace message will be a synchronization message. 22-56 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 989 Max Length = 64 bits Min Length = 16 bits Figure 22-45. Data Write Synchronization Message Format 22.4.2.5 Data Read Synchronization Messaging The data read synchronization message has the following format: MOTOROLA Chapter 22. READI Module 22-57 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 990 DC register and the DTA registers. For details on field configuration, refer to Section 22.1.1.4, “Development Control Register (DC),” and Section 22.1.1.9, “Data Trace Attributes 1 and 2 Registers (DTA1 and DTA2),” respectively. 22-58 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 991 Data Trace Windowing Data trace windowing is achieved via the address range within the DTEA and the DTSA fields of the DTA registers. All L-bus accesses which fall within these two address ranges, MOTOROLA Chapter 22. READI Module 22-59 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 992 Cycle captured and transmitted L-bus Cycle initiated by READI (Read/Write Access) Cycle ignored L-bus Cycle is an instruction fetch Cycle ignored Data Storage Interrupt Cycle ignored System Reset Cycle ignored 22-60 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 993 Therefore, the average number of data trace messages that can be transmitted out is 6.2 million (1/161ns) per second, or 24.8 million bytes of read/write data per second. MOTOROLA Chapter 22. READI Module 22-61...
Page 994 MDO[7:0] TCODE = 13 (0xD) Don’t care data Number of messages cancelled = 0 (idle clock) Full target address = 0x1468ACE Data = 0xBE Figure 22-51. Data Write Synchronization Message 22-62 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 995 (UDI) via the four auxiliary access public messages: device ready for upload/download, upload request (tool requests information), download request (tool provides information), upload/download information (device/tool provides information). MOTOROLA Chapter 22. READI Module 22-63 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 996 Min Length = 22 bits Figure 22-56. Write Register Message [8-80 bits] [6 bits] TCODE (19) Return Value Max Length = 86 bits Min Length = 14 bits Figure 22-57. Read/Write Response Message 22-64 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 997 Device sends to Tool CNT= 0 SC = 0 Decrement CNT Increment Address Read Write Read/Write Upload/Download Information Public Message (TCODE 19) Tool sends to Device Figure 22-58. Read/Write Access Flow Diagram MOTOROLA Chapter 22. READI Module 22-65 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 998 2. The download request public message contains: a) TCODE(18) b) Access opcode 0xF which signals that subsequent data needs to be stored in the RWA register. c) Configure the RWA register fields as follows 22-66 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 999 18) should not be used to write subsequent data to the UDI register. Data written to the UDI register (via download request message, TCODE 18) is not used by the device for any read/write operation. MOTOROLA Chapter 22. READI Module 22-67 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...
Page 1000 (TCODE = 18). 2. The download request public message contains: a) TCODE(18) b) Access opcode 0xF which signals that subsequent data needs to be stored in the RWA register. 22-68 MPC533 Reference Manual MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE...

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