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Functional Description
Pin(s) Affected
Clock mode
A[23:21]/CS[6:4]
1
Modifying the default configurations is possible only if the external RCON pin is asserted.
2
The D[31:27, 23:22, 20, 15:0] pins do not affect reset configuration.
3
The external reset override circuitry drives the data bus pins with the override values while RSTO is asserted. It must stop driving the data
bus pins within one CLKOUT cycle after RSTO is negated. To prevent contention with the external reset override circuitry, the reset
override pins are forced to inputs during reset and do not become outputs until at least one CLKOUT cycle after RSTO is negated.
4
RCON[0] has higher priority than RCON[3:2]. When RCON[0] is configured to boot the chip in single chip mode, the part will boot
internally with a 32-bit port overriding any configuration set by RCON[3:2].
5
Default configuration
30.6.2 Chip Mode Selection
The chip mode is selected during reset and reflected in the MODE field of the chip
configuration register (CCR). See Section 30.5.3.1, "Chip Configuration Register (CCR)."
Once reset is exited, the operating mode cannot be changed. Table 30-11 shows the mode
selection during reset configuration.
When Flash security is enabled, the chip will boot in single
chip mode regardless of the external reset configuration.
30-10
Table 30-10. Configuration During Reset
Default
Configuration
RCON[7:6] = 11
RCON[9:8] = 00
MCF5282 User's Manual
1
(continued)
Override Pins
2, 3 4
in Reset
CLKMOD1,
CLKMOD0
00
01
10
11
D[25:24]
00
10
01
11
NOTE
Function
Clock Mode
External clock mode (PLL disabled)
1:1 PLL mode
Normal PLL mode with external
clock reference
Normal PLL mode w/crystal reference
Chip Select Configuration
5
PF[7:5] = A[23:21]
PF[7] = CS6 / PF[6:5] = A[22:21]
PF[7:6] = CS6, CS5 / PF[5] = A[21]
PF[7:6] = CS6, CS5, CS4
MOTOROLA
5
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