I2Fdr Field Descriptions - Motorola ColdFire MCF5281 User Manual

2
24.5.2 I C Frequency Divider Register (I2FDR)
The I2FDR, shown in Figure 24-6, provides a programmable prescaler to configure the I
clock for bit-rate selection.
Field
Reset
R/W
Address
Figure 24-6. I
Table 24-3 describes I2FDR[IC].
Bits Name
7–6 — Reserved, should be cleared.
2
5–0 IC I C clock rate. Prescales the clock for bit-rate selection. Due to potentially slow SCL and SDA rise and fall times,
bus signals are sampled at the prescaler frequency. The serial bit clock frequency is equal to the system clock
divided by the divider shown below.
IC
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
MOTOROLA
7 6 5
—
0000_0000
IPSBAR + 0x304
2
C Frequency Divider Register (I2FDR)
Table 24-3. I2FDR Field Descriptions
Divider IC Divider
28 0x10 288
30 0x11 320
34 0x12 384
40 0x13 480
44 0x14 576
48 0x15 640
56 0x16 768
68 0x17 960
80 0x18 1152
88 0x19 1280
104 0x1A 1536
128 0x1B 1920
144 0x1C 2304
160 0x1D 2560
192 0x1E 3072
240 0x1F 3840
Chapter 24. I
IC
R/W
Description
IC Divider
0x20 20
0x21 22
0x22 24
0x23 26
0x24 28
0x25 32
0x26 36
0x27 40
0x28 48
0x29 56
0x2A 64
0x2B 72
0x2C 80
0x2D 96
0x2E 112
0x2F 128
2
C Interface
Programming Model
2
C
0
IC Divider
0x30 160
0x31 192
0x32 224
0x33 256
0x34 320
0x35 384
0x36 448
0x37 512
0x38 640
0x39 768
0x3A 896
0x3B 1024
0x3C 1280
0x3D 1536
0x3E 1792
0x3F 2048
24-7