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The STOP instruction has the following effects:
1. The instruction before the STOP executes and then generates a trace exception. In
the exception stack frame, the PC points to the STOP opcode.
2. When the trace handler is exited, the STOP instruction is executed, loading the SR
with the immediate operand from the instruction.
3. The processor then generates a trace exception. The PC in the exception stack
frame points to the instruction after the STOP, and the SR reflects the value loaded
in the previous step.
If the processor is not in trace mode and executes a STOP instruction where the immediate
operand sets SR[T], hardware loads the SR and generates a trace exception. The PC in the
exception stack frame points to the instruction after the STOP, and the SR reflects the value
loaded in step 2.
Because ColdFire processors do not support any hardware stacking of multiple exceptions,
it is the responsibility of the operating system to check for trace mode after processing other
exception types. As an example, consider the execution of a TRAP instruction while in
trace mode. The processor will initiate the TRAP exception and then pass control to the
corresponding handler. If the system requires that a trace exception be processed, it is the
responsibility of the TRAP exception handler to check for this condition (SR[15] in the
exception stack frame asserted) and pass control to the trace handler before returning from
the original exception.
2.7.7
Unimplemented Line-A Opcode
A line-A opcode is defined when bits 15-12 of the opword are 0b1010. This exception is
generated by the attempted execution of an undefined line-A opcode.
2.7.8
Unimplemented Line-F Opcode
A line-F opcode is defined when bits 15-12 of the opword are 0b1111. This exception is
generated by attempted execution of an undefined line-F opcode.
2.7.9
Debug Interrupt
This special type of program interrupt is discussed in detail in Chapter 29, "Debug
Support." This exception is generated in response to a hardware breakpoint register trigger.
The processor does not generate an IACK cycle but rather calculates the vector number
internally (vector number 12).
MOTOROLA
Chapter 2. ColdFire Core
Processor Exceptions
2-15
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