Section 4 Modes Of Operation; Overview; Chip Configuration Summary; Table 4-1 Mode Selection - Motorola MC9S12DT256 User Manual

Section 4 Modes of Operation

4.1 Overview

Eight possible modes determine the operating configuration of the MC9S12DT256. Each mode has an
associated default memory map and external bus configuration controlled by a further pin.
Three low power modes exist for the device.

4.2 Chip Configuration Summary

The operating mode out of reset is determined by the states of the MODC, MODB, and MODA pins during
reset (Table 4-1). The MODC, MODB, and MODA bits in the MODE register show the current operating
mode and provide limited mode switching during operation. The states of the MODC, MODB, and MODA
pins are latched into these bits on the rising edge of the reset signal. The ROMCTL signal allows the setting
of the ROMON bit in the MISC register thus controlling whether the internal Flash is visible in the
memory map. ROMON = 1 mean the Flash is visible in the memory map. The state of the ROMCTL pin
is latched into the ROMON bit in the MISC register on the rising edge of the reset signal.
BKGD = PE6 =
MODC MODB
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
For further explanation on the modes refer to the Core User Guide.

Table 4-1 Mode Selection

PE5 = PK7 =
MODA ROMCTL
0 X
0
1
1
0 X
0
1
1
0 X
0
1
1
0 X
0
1
1

Table 4-2 Clock Selection Based on PE7

PE7 = XCLKS
1
Colpitts Oscillator selected
MC9S12DT256 Device User Guide — V03.07
ROMON
Bit
Special Single Chip, BDM allowed and ACTIVE. BDM is
1 allowed in all other modes but a serial command is
required to make BDM active.
1
Emulation Expanded Narrow, BDM allowed
0
0
Special Test (Expanded Wide), BDM allowed
1
Emulation Expanded Wide, BDM allowed
0
1
Normal Single Chip, BDM allowed
0
Normal Expanded Narrow, BDM allowed
1
Peripheral; BDM allowed but bus operations would cause
1
bus conflicts (must not be used)
0
Normal Expanded Wide, BDM allowed
1
Description
Mode Description
71