Dma Timer Mode Registers (Dtmrn); Dtmrn Bit Definitions - Motorola ColdFire MCF5281 User Manual

DMA Timer Programming Model
Table 21-1. DMA Timer Module Memory Map (continued)
IPSBAR
[31:24]
Offset
0x448
0x44C
DMA Timer2 Mode Register (TMR2)
0x480
0x484
0x488
0x48C
DMA Timer3 Mode Register (TMR3)
0x4C0
0x4C4
0x4C8
0x4CC

21.2.6 DMA Timer Mode Registers (DTMRn)

DTMRs, shown in Figure 21-2, program the prescaler and various timer modes.
15
Field
Reset
R/W
Address IPSBAR + 0x400 (DTMR0); + 0x440 (DTMR1); + 0x480 (DTMR2); + 0x4C0 (DTMR3)
21-4
[23:16]
DMA Timer1 Capture Register (DTCR1)
DMA Timer1 Counter Register (DTCN1)
DMA Timer2 Reference Register (DTRR2)
DMA Timer2 Capture Register (DTCR2)
DMA Timer2 Counter Register (DTCN2)
DMA Timer3 Reference Register (DTRR3)
DMA Timer3 Capture Register (DTCR3)
DMA Timer3 Counter Register (DTCN3)
8
PS
0000_0000_0000_0000
R/W
Figure 21-2. DTMRn Bit Definitions
MCF5282 User's Manual
[15:8]
DMA Timer2 Extended
Mode Register (DTXMR2)
DMA Timer3 Extended
Mode Register (DTXMR3)
7 6 5 4 3
CE OM ORRI FRR
[7:0]
DMA Timer2 Event
Register (DTER2)
DMA Timer3 Event
Register (DTER3)
2 1 0
CLK RST
MOTOROLA