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Bit(s)
Name
7–4
—
3–0
OC3M
20.5.4 GPT Output Compare 3 Data Register (GPTOC3D)
Field
Reset
R/W
Address
Figure 20-5. GPT Output Compare 3 Data Register (GPTOC3D)
Bit(s)
Name
7–4
—
3–0
OC3D
A successful channel 3 output compare overrides any channel
2:0 compares. For each OC3M bit that is set, the output
compare action reflects the corresponding OC3D bit.
20.5.5 GPT Counter Register (GPTCNT)
15
Field
Reset
R/W
Address
MOTOROLA
Chapter 20. General Purpose Timer Modules (GPTA and GPTB)
Table 20-6. GPTOC3M Field Descriptions
Reserved, should be cleared.
Output compare 3 mask. Setting an OC3M bit configures the corresponding PORTTn
pin to be an output. OC3Mn makes the GPT port pin an output regardless of the data
direction bit when the pin is configured for output compare (IOSx = 1). The OC3Mn bits
do not change the state of the PORTTnDDR bits. These bits are read anytime, write
anytime.
1 Corresponding PORTTn pin configured as output
0 No effect
7
—
IPSBAR + 0x1A_0003, 0x1B_0003
Table 20-7. GPTOC3D Field Descriptions
Reserved, should be cleared.
Output compare 3 data. When a successful channel 3 output compare occurs, these
bits transfer to the PORTTn data register if the corresponding OC3Mn bits are set.
These bits are read anytime, write anytime.
0000_0000_0000_0000
IPSBAR + 0x1A_0004, 0x1B_0004
Figure 20-6. GPT Counter Register (GPTCNT)
Description
4
3
0000_0000
R/W
Description
NOTE
CNTR
Read only
Memory Map and Registers
0
OC3D
0
20-7
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