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3. The last clock of the bus cycle uses what would be an idle clock between cycles to
provide hold time for address, attributes and write data. Figure 13-6 and Figure 13-8
show the basic read and write operations.
13.4.2 Data Transfer Cycle States
The data transfer operation in the MCF5282 is controlled by an on-chip state machine. Each
bus clock cycle is divided into two states. Even states occur when CLKOUT is high and
odd states occur when CLKOUT is low. The state transition diagram for basic and fast
termination read and write cycles are shown in Figure 13-4.
Figure 13-4. Data Transfer State Transition Diagram
Table 13-3 describes the states as they appear in subsequent timing diagrams.
State
Cycle
CLKOUT
S0
All
High
S1
All
Low
Fast
Termination
S2
Read/write
High
(skipped fast
termination)
Write
MOTOROLA
Next Cycle
S0
S5
Fast
Termination
S4
S3
Table 13-3. Bus Cycle States
The read or write cycle is initiated in S0. On the rising edge of CLKOUT, the
MCF5282 places a valid address on the address bus and drives R/W high for a
read and low for a write, if it is not already in the appropriate state. The MCF5282
asserts TIP, SIZ[1:0], and TS on the rising edge of CLKOUT.
The appropriate CSn, BS, and OE signals assert on the CLKOUT falling edge.
TA must be asserted during S1. Data is made available by the external device
and is sampled on the rising edge of CLKOUT with TA asserted.
TS is negated on the rising edge of CLKOUT in S2.
The data bus is driven out of high impedance as data is placed on the bus on the
rising edge of CLKOUT.
Chapter 13. External Interface Module (EIM)
S1
Basic
Read/Write
S2
Wait
States
Description
Data Transfer Operation
13-5
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