Overview; Arbitration Algorithms - Motorola ColdFire MCF5281 User Manual

Motorola microcontroller user's manual
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8.5.1

Overview

The basic functionality is that of a 4-port, pipelined internal bus arbitration module with the
following attributes:
• The master pointed to by the current arbitration pointer may get on the bus with zero
latency if the address phase is available. All other requesters face at least a one cycle
arbitration pipeline delay in order to meet bus timing constraints on address phase
hold.
• If a requester will get an immediate address phase (that is, it is pointed to by the
current arbitration pointer and the bus address phase is available), it will be the
current bus master and is ignored by arbitration. All remaining requesting ports are
evaluated by the arbitration algorithm to determine the next-state arbitration pointer.
• There are two arbitration algorithms, fixed and round-robin. Fixed arbitration sets
the next-state arbitration pointer to the highest priority requester. Round-robin
arbitration sets the next-state arbitration pointer to the highest priority requester
(calculated by adding a requester's fixed priority to the current bus master's fixed
priority and then taking this sum modulo the number of possible bus masters).
• The default priority is FEC (M3) > DMA (M2) > internal master (M1) > CPU (M0),
where M3 is the highest and M0 the lowest priority.
• There are two actions for an idle arbitration cycle, either leave the current arbitration
pointer as is or set it to the lowest priority requester.
• The anti-lock-out logic for the fixed priority scheme forces the arbitration algorithm
to round-robin if any requester has been held for longer than a specified cycle count.
8.5.2

Arbitration Algorithms

There are two modes of arbitration: fixed and round-robin. This section discusses the
differences between them.
8.5.2.1
Round-Robin Mode
Round-robin arbitration is the default mode after reset. This scheme cycles through the
sequence of masters as specified by MPARK[Mn_PRTY] bits. Upon completion of a
transfer, the master is given the lowest priority and the priority for all other masters is
increased by one.
M3 = 11 M2 =01 M1 = 10 M0 = 00
next +1
M3 = 00 M2 =10 M1 = 11 M0 = 01
next +2
M3 = 01 M2 =11 M1 = 00 M0 = 10
next +3
M3 = 10 M2 =00 M1 = 01 M0 = 11
MOTOROLA
Chapter 8. System Control Module (SCM)
Internal Bus Arbitration
8-11

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