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Cache Physical Organization
array address. The tag array outputs the address mapped to the given cache location along
with the valid bit for the line. This address field is compared to bits [31:11] for instruction-
or data-only configurations and to bits [31:10] for a split configuration of the fetch address
from the local bus to determine if a cache hit has occurred. If the desired address is mapped
into the cache memory, the output of the storage array is driven onto the ColdFire core's
local data bus, thereby completing the access in a single cycle.
The tag array maintains a single valid bit per line entry. Accordingly, only entire 16-byte
lines are loaded into the cache.
The cache also contains separate 16-byte instruction and data line-fill buffers that provide
temporary storage for the last line fetched in response to a cache miss. With each fetch, the
contents of the associated line fill buffer are examined. Thus, each fetch address examines
both the tag memory array and the associated line fill buffer to see if the desired address is
mapped into either hardware resource. A cache hit in either the memory array or the
associated line-fill buffer is serviced in a single cycle. Because the line fill buffer maintains
valid bits on a longword basis, hits in the buffer can be serviced immediately without
waiting for the entire line to be fetched.
If the referenced address is not contained in the memory array or the associated line-fill
buffer, the cache initiates the required external fetch operation. In most situations, this is a
16-byte line-sized burst reference.
The hardware implementation is a nonblocking design, meaning the ColdFire core's local
bus is released after the initial access of a miss. Thus, the cache or the SRAM module can
service subsequent requests while the remainder of the line is being fetched and loaded into
the fill buffer.
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MCF5282 User's Manual
MOTOROLA
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