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Modes of Operation
• Automatic internal flushing of the receive FIFO for runts (collision fragments) and
address recognition rejects (no processor bus utilization)
• Address recognition
— Frames with broadcast address may be always accepted or always rejected
— Exact match for single 48-bit individual (unicast) address
— Hash (64-bit hash) check of individual (unicast) addresses
— Hash (64-bit hash) check of group (multicast) addresses
— Promiscuous mode
17.2 Modes of Operation
The primary operational modes are described in this section.
17.2.1 Full and Half Duplex Operation
Full duplex mode is intended for use on point to point links between switches or end node
to switch. Half duplex mode is used in connections between an end node and a repeater or
between repeaters. Selection of the duplex mode is controlled by TCR[FDEN].
When configured for full duplex mode, flow control may be enabled. Refer to the
TCR[RFC_PAUSE] and TCR[TFC_PAUSE] bits, the RCR[FCE] bit, and Section 17.4.10,
"Full Duplex Flow Control," for more details.
17.2.2 Interface Options
The following interface options are supported. A detailed discussion of the interface
configurations is provided in Section 17.4.5, "Network Interface Options".
17.2.2.1 10 Mbps and 100 Mbps MII Interface
MII is the Media Independent Interface defined by the IEEE 802.3 standard for 10/100
Mbps operation. The MAC-PHY interface may be configured to operate in MII mode by
asserting RCR[MII_MODE].
The speed of operation is determined by the ETXCLK and ERXCLK pins which are driven
by the external transceiver. The transceiver will either auto-negotiate the speed or it may be
controlled by software via the serial management interface (EMDC/EMDIO pins) to the
transceiver. Refer to the MMFR and MSCR register descriptions as well as the section on
the MII for a description of how to read and write registers in the transceiver via this
interface.
17-2
MCF5282 User's Manual
MOTOROLA
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