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Memory Map/Register Definition
26.3.2.5 Port B/C/D Pin Assignment Register (PBCDPAR)
The PBCDPAR controls the pin function of ports B, C, and D.
The PBCDPAR register is read/write.
7
Field
PBPA
1
Reset See Note 1
R/W:
R/W
Address
Figure 26-18. Port B/C/D Pin Assignment Register (PBCDPAR)
1
Reset state determined during reset configuration as shown in Table 26-8.
Bits
7
6
5–0
Mode of Operation
Master mode
Single chip mode
1
Note if the port size of the external boot device is less than the port size of the
external SDRAM, the PBCDPAR register must be written after reset to enable
the primary function(s) on ports B,C, and D, before any SDRAM accesses are
attempted.
26-14
6
5
PCDPA
See Note 1
R/W
IPSBAR + 0x10_0050
Table 26-7. PBCDPAR Field Descriptions
Name
PBPA
Port B pin assignment. Configures the port B pins for their primary function
(D[23:16]) or digital I/O.
1 Port B pins configured for primary function (D[23:16])
0 Port B pins configured for digital I/O
PCDPA
Ports C,D pin assignment. Configures the port C and D pins for their primary
functions (D[15:8], D[7:0]) or digital I/O.
1 Port C,D pins configured for primary function (D[15:8], D[7:0])
0 Port C,D pins configured for digital I/O
—
Reserved, should be cleared.
Table 26-8. Reset Values for PBCDPAR Bits
Port Size of
External Boot
1
Device
8-bit
16-bit
32-bit
N/A
MCF5282 User's Manual
—
00_0000
R
Description
PBPA Reset
PCDPA Reset
Value
Value
0
0
1
0
1
1
0
0
0
MOTOROLA
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