Receive Bdm Packet; Transmit Bdm Packet; Receive Bdm Packet Field Description; Transmit Bdm Packet Field Description - Motorola ColdFire MCF5281 User Manual

Motorola microcontroller user's manual
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A not-ready response can be ignored except during a
memory-referencing cycle. Otherwise, the debug module can
accept a new serial transfer after 32 processor clock periods.
29.5.2.1 Receive Packet Format
The basic receive packet, Figure 29-13, consists of 16 data bits and 1 status bit
.
16
15
S
Table 29-15 describes receive BDM packet fields.
Table 29-15. Receive BDM Packet Field Description
Bits
Name
16
S
Status. Indicates the status of CPU-generated messages listed below. The not-ready response can be ignored
unless a memory-referencing cycle is in progress. Otherwise, the debug module can accept a new serial transfer
after 32 processor clock periods.
S
Data
0
xxxx
0
0xFFFF
1
0x0000
1
0x0001
1
0xFFFF
15–0
D
Data. Contains the message to be sent from the debug module to the development system. The response
message is always a single word, with the data field encoded as shown above.
29.5.2.2 Transmit Packet Format
The basic transmit packet, Figure 29-14, consists of 16 data bits and 1 control bit.
16
15
C
Table 29-16 describes transmit BDM packet fields.
Table 29-16. Transmit BDM Packet Field Description
Bits
Name
16
C
Control. This bit is reserved. Command and data transfers initiated by the development system should clear C.
15–0
D
Data bits 15–0. Contains the data to be sent from the development system to the debug module.
MOTOROLA
NOTE:
Data Field [15:0]
Figure 29-13. Receive BDM Packet
Message
Valid data transfer
Status OK
Not ready with response; come again
Error—Terminated bus cycle; data invalid
Illegal command
Figure 29-14. Transmit BDM Packet
Chapter 29. Debug Support
Background Debug Mode (BDM)
Description
D
Description
0
0
29-19

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