Watchdog Control Register (Wcr); Registers; Watchdog Timer Module Memory Map - Motorola ColdFire MCF5281 User Manual

Table 18-2. Watchdog Timer Module Memory Map
IPSBAR Offset
0x0014_0000
0x0014_0002
0x0014_0004
0x0014_0006
1
S = CPU supervisor mode access only. S/U = CPU supervisor or user mode access. User mode accesses
to supervisor only addresses have no effect and result in a cycle termination transfer error.

18.5.2 Registers

The watchdog timer programming model consists of these registers:
• Watchdog control register (WCR), which configures watchdog timer operation
• Watchdog modulus register (WMR), which determines the timer modulus
reload value
• Watchdog count register (WCNTR), which provides visibility to the watchdog
counter value
• Watchdog service register (WSR), which requires a service sequence to
prevent reset

18.5.2.1 Watchdog Control Register (WCR)

The 16-bit WCR configures watchdog timer operation.
15
Field
Reset
R/W
7
Field
Reset
R/W
Address
MOTOROLA
Bits 15–8
Watchdog Control Register (WCR)
Watchdog Modulus Register (WMR)
Watchdog Count Register (WCNTR)
Watchdog Service Register (WSR)
14 13
6 5
—
R
IPSBAR + 0x0014_0000, 0x0014_0001
Figure 18-2. Watchdog Control Register (WCR)
Chapter 18. Watchdog Timer Module
Bits 7–0
12 11
—
0000_0000
R
4 3
WAIT DOZE
0000_1111
Memory Map and Registers
1
Access
S
S
S/U
S/U
10 9 8
2 1 0
HALTED EN
R/W
18-3