Reset Configuration Register (Rcon); Rcon Field Descriptions - Motorola ColdFire MCF5281 User Manual

Memory Map and Registers
Bits Name
3 BME Bus monitor enable. This read/write bit enables the bus monitor to operate during external bus cycles.
0 Bus monitor disabled for external bus cycles.
1 Bus monitor enabled for external bus cycles.
Table 30-2 shows the read/write accessibility of this write-once bit.
2–0 BMT Bus monitor timing. This field selects the timeout period (in system clocks) for the bus monitor.
000 65536
001 32768
010 16384
011 8192
100 4096
101 2048
110 1024
111 512
Table 30-2 shows the read/write accessibility of this write-once bit.

30.5.3.2 Reset Configuration Register (RCON)

At reset, RCON determines the default operation of certain chip functions. All default
functions defined by the RCON values can only be overridden during reset configuration
(see Section 30.6.1, "Reset Configuration") if the external RCON pin is asserted. RCON is
a read-only register.
15
Field —
Reset
R/W
Address
Bits Name
15–10 —
9–8 RCSC
7 RPLLSEL
30-6
Table 30-4. CCR Field Descriptions (continued)
10 9 8 7
RCSC RPLLSEL RPLLREF RLOAD
Figure 30-3. Reset Configuration Register (RCON)
Table 30-5. RCON Field Descriptions
Reserved, should be cleared.
Chip select configuration. Reflects the default chip select configuration. The default function of the
chip select configuration can be overridden during reset configuration. See Table 30-6 for bit
encodings.
PLL mode select. Reflects the default PLL mode.
0 1:1 PLL mode
1 Normal PLL mode (This is the value used for the MCF5282.)
The default PLL mode can be overridden during reset configuration. If the default is overridden, the
clock module's SYNSR[PLLSEL] bit reflects the PLL mode.
MCF5282 User's Manual
Description
6 5
0000_0000_1110_0000
R
IPSBAR + 0x11_0008
Description
4 3 2
BOOTPS BOOTSEL
MOTOROLA
1 0
— MODE