Branch Instruction Execution Times; Coldfire Instruction Set Architecture Enhancements; General Branch Instruction Execution Times; Bra, Bcc Instruction Execution Times - Motorola ColdFire MCF5281 User Manual

Branch Instruction Execution Times

The execution times for moving the contents of the Racc,
Raccext[01,23], MACSR, or Rmask into a destination location
<ea>x shown in this table represent the best-case scenario
when the store instruction is executed and there are no load or
M{S}AC instructions in the EMAC execution pipeline. In
general, these store operations require only a single cycle for
execution, but if preceded immediately by a load, MAC, or
MSAC instruction, the depth of the EMAC pipeline is exposed
and the execution time is four cycles.
2.13 Branch Instruction Execution Times
Table 2-17. General Branch Instruction Execution Times
Opcode <EA>
Rn
bsr —
jmp <ea> —
jsr <ea> —
rte —
rts —
Table 2-18. BRA, Bcc Instruction Execution Times
Opcode
bra
bcc
2.14 ColdFire Instruction Set Architecture
Enhancements
This section describes the new opcodes implemented as part of the Revision A+
enhancements to the basic ColdFire ISA.
2-28
NOTE
Effective Address
(An) (An)+ -(An)
— — —
3(0/0) — —
3(0/1) — —
— 10(2/0) —
— 5(1/0) —
Forward Forward
Taken Not Taken
2(0/0) —
3(0/0) 1(0/0)
MCF5282 User's Manual
(d16,An) (d8,An,Xi*SF)
(d16,PC) (d8,PC,Xi*SF)
3(0/1) —
3(0/0) 4(0/0)
3(0/1) 4(0/1)
— —
— —
Backward Backward
Taken Not Taken
2(0/0) —
2(0/0) 3(0/0)
xxx.wl #xxx
— —
3(0/0) —
3(0/1) —
— —
— —
MOTOROLA