General Synchronous Operation Guidelines; Generic Address Multiplexing Scheme - Motorola ColdFire MCF5281 User Manual

15.2.3 General Synchronous Operation Guidelines

To reduce system logic and to support a variety of SDRAM sizes, the DRAM controller
provides SDRAM control signals as well as a multiplexed row address and column address
to the SDRAM.
15.2.3.1 Address Multiplexing
Table 15-7 shows the generic address multiplexing scheme for SDRAM configurations. All
possible address connection configurations can be derived from this table.
Because the MCF5282 has 24 extermal address lines, the
maximum SDRAM address size is 128 Mbits.
The following tables provide a more comprehensive, step-by-step way to determine the
correct address line connections for interfacing the MCF5282 to the SDRAM. To use the
tables, find the one that corresponds to the number of column address lines on the SDRAM
and to the port size as seen by the MCF5282, which is not necessarily the SDRAM port size.
For example, if two 1M x 16-bit SDRAMs together form a 1M x 32-bit memory, the port
size is 32 bits. Most SDRAMs likely have fewer address lines than are shown in the tables,
so follow only the connections shown until all SDRAM address lines are connected.
Address Pin Row Address
17 17
16 16
15 15
14 14
13 13
12 12
11 11
10 10
9 9
17 17
18 18
19 19
20 20
21 21
22 22
23 23
MOTOROLA
Table 15-7. Generic Address Multiplexing Scheme
Column Address
0
1
2
3
4
5
6
7
8
16
17
18
19
20
21
22
Chapter 15. Synchronous DRAM Controller Module
NOTE
Notes Relating to Port Sizes
8-bit port only
8- and 16-bit ports only
32-bit port only
16-bit port only or 32-bit port with only 8 column address lines
16-bit port only when at least 9 column address lines are used
SDRAM Controller Operation
15-9