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DMA Timer Programming Model
System Clock
)
(÷1 or ÷16
DTINn
Capture
Detection
31
DMA Timer Capture Register (DTCRn)
(latches DTCN value when triggered by DTINn)
DTOUTn
IRQn
DREQn
21.1.1 Key Features
Each DMA timer module has the following features:
• Maximum timeout period of 266,521 seconds at 66 MHz (~74 hours)
• 15-ns resolution at 66 MHz
• Programmable sources for the clock input, including external clock
• Programmable prescaler
• Input-capture capability with programmable trigger edge on input pin
• Programmable mode for the output pin on reference compare
• Free run and restart modes
• Programmable interrupt or DMA request on input capture or reference-compare
21.2 DMA Timer Programming Model
The following features are programmable through the timer registers, shown in Table 21-1:
21.2.1 Prescaler
The prescaler clock input is selected from system clock (divided by 1 or 16) or from the
corresponding timer input, DTINn. DTINn is synchronized to the system clock. The
synchronization delay is between two and three system clocks. The corresponding
21-2
15
DMA Timer Mode Register (DTMRn)
DMA Timer
Prescaler
Clock
Generator
clock
31
DMA Timer Counter Register (DTCNn)
(contains incrementing value)
7
DMA Timer Event Register (DTERn)
(indicates capture or when DTCN = DTRRn)
Figure 21-1. DMA Timer Block Diagram
MCF5282 User's Manual
0
Mode Bits
Divider
0
0
31
DMA Timer Reference Register (DTRRn)
(reference value for comparison with DTCN)
0
7
0
DMA Timer Extended Mode
Register (DTXMRn)
0
MOTOROLA
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