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Memory Map/Register Definition
7
Field
—
Reset
R/W:
R
Address
7
Field
—
Reset
R/W:
R
Address
7
Field
Reset
R/W:
Address
Table 26-4. DDRn (8-bit, 6-bit, and 4-bit) Field Descriptions
Register
8-bit
7-bit
6-bit
4-bit
7-bit
6-bit
4-bit
26-10
6
DDRn6
DDRn5
IPSBAR + 0x10_0021(DDRQS)
Figure 26-7. Port Data Direction Register (7-bit)
6
5
DDRn5
IPSBAR + 0x10_0020 (DDRAS), 0x10_0022 (DDRSD)
Figure 26-8. Port Data Direction Registers (6-bit)
—
R
IPSBAR + 0x10_0023 (DDRTC), 0x10_0024 (DDRTD), 0x10_0025 (DDRUA)
Figure 26-9. Port Data Direction Registers (4-bit)
Bits
Name
7–0
DDRnx
6–0
5–0
3–0
7
—
7–6
7–4
MCF5282 User's Manual
DDRn4
DDRn3
DDRn2
0000_0000
R/W
4
3
DDRn4
DDRn3
DDRn2
0000_0000
R/W
4
3
DDRn3
DDRn2
0000_0000
Port n data direction bits.
1 Port n pin configured as an output
0 Port n pin configured as an input
Reserved, should be cleared.
0
DDRn1
DDRn0
2
1
0
DDRn1
DDRn0
2
1
0
DDRn1
DDRn0
R/W
Description
MOTOROLA
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