Table of Contents
Advertisement
CLKOUT
SRAS
SCAS
DRAMW
SDRAM_CS[0] or [1]
SCKE
(DCR[COC] = 0)
15.2.4 Initialization Sequence
Synchronous DRAMs have a prescribed initialization sequence. The DRAM controller
supports this sequence with the following procedure:
1. SDRAM control signals are reset to idle state. Wait the prescribed period after reset
before any action is taken on the SDRAMs. This is normally around 100 µs.
2. Initialize the DCR, DACR, and DMR in their operational configuration. Do not yet
enable
or
PALL
3. Issue a
command to the SDRAMs by setting DACR[IP] and accessing a
PALL
SDRAM location. Wait the time (determined by t
4. Enable refresh (set DACR[RE]) and wait for at least 8 refreshes to occur.
5. Before issuing the
modified to allow the
6. Issue the
MRS
SDRAM. Note that mode register settings are driven on the SDRAM address bus,
so care must be taken to change DMR[BAM] if the mode register configuration
does not fall in the address range determined by the address mask bits. After the
mode register is set, DMR mask bits can be restored to their desired configuration.
MOTOROLA
t
= 2
RCD
PALL
SELF
Self-
Refresh
Active
Figure 15-9. Self-Refresh Operation
commands.
REF
command, determine if the DMR mask bits need to be
MRS
to execute properly
MRS
command by setting DACR[IMRS] and accessing a location in the
Chapter 15. Synchronous DRAM Controller Module
SELFX
) before any other execution.
RP
SDRAM Controller Operation
t
= 6
RC
First
Possible
ACTV
15-17
Advertisement
Table of Contents
