Resets And Power Down; Pcs Reset; Pcs/Pma Power Down; Table 3-6: Power Control Descriptions - Xilinx RocketIO X User Manual

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Table 3-5: Latency Through Various Receiver Components/Processes (Continued)
Block
No Clock 3 RXCLK0 +
Correction 10 RXUSRCLK
(3)
Min/Max Used 3 RXCLK0 +
1 RXUSRCLK + (MIN_LAT/4) < latency < 3 RXCLK0 + 1 RXUSRCLK + (MAX_LAT/4)
(4)
Fabric Interface 1 RXUSRCLK +
2 RXUSRCLK2
(5)
Worst Case Total 12 RXCLK0, (5 +
MAX_LAT/4)
RXUSRCLK,
2 RXUSRCLK2
(5)
Best Case Total 9 RXCLK0,
(4 + MIN_LAT/4)
RXUSRCLK,
2 RXUSRCLK2
Notes:
1. 4-byte mode can be run with internal data width of 2 or 4 byte. If 2 byte (lower serial speeds), the 3-clock delay must be used;
otherwise 2-clock delay can be used (approx. clock cycles).
2. RXCLK0 is equal in frequency to the RXUSRCLK.
3. Clock correction must be enabled to use this feature.
4. Fabric interface has delays in both clock domains. The ratio between these two is shown in
5. Approximate latency when worst/best case latency for each block is used.

Resets and Power Down

In the PCS, there are several reset and power down functions that have different effects. It
is possible to only reset the PCS, which brings every flop in the PCS to a known value, but
does not affect the PMA configuration. It is also possible to reset the PCS and at the same
time re-initialize the PMA function, which would reload the PMA coefficients.

PCS Reset

When the signals TXRESET or RXRESET are asserted High, the PCS is considered in reset.
After the signal that caused the reset is asserted Low, the PCS takes five clocks to come out
of reset for each clock domain.
The PMA configuration vector is not affected during this reset, so the PMA speed, filter
settings, and so on, all remain intact. Also, the PMA internal pipeline is not affected and
continues to operate in normal fashion.

PCS/PMA Power Down

The POWERDOWN signal controls power down within the PCS and PMA. The following
table describes the function of the POWERDOWN bus.

Table 3-6: Power Control Descriptions

90
1 Byte 2 Byte
1 RXUSRCLK +
1 RXUSRCLK2
12 RXCLK0, (5 +
MAX_LAT/4)
RXUSRCLK,
1 RXUSRCLK2
9 RXCLK0,
(4 + MAX_LAT/4)
RXUSRCLK,
1 RXUSRCLK2
POWERDOWN
0
1
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Chapter 3: Clocking and Clock Domains
4 Byte
1-2 RXUSRCLK +
1 RXUSRCLK2
12 RXCLK0, (6 +
MAX_LAT/4)
RXUSRCLK,
1 RXUSRCLK2
9 RXCLK0,
(6 + MAX_LAT/4)
RXUSRCLK,
1 RXUSRCLK2
Table 3-3.
Function
PCS and PMA function normally
PMA and PCS in powerdown mode
RocketIO™ X Transceiver User Guide
UG035 (v1.5) November 22, 2004
8 Byte
2 RXUSRCLK +
1 RXUSRCLK2
12 RXCLK0, (6 +
MAX_LAT/4)
RXUSRCLK,
1 RXUSRCLK2
9 RXCLK0,
(4 + MAX_LAT/4)
RXUSRCLK,
1 RXUSRCLK2