Chapter 1: Transceiver And Tool Overview; Overview - Xilinx Virtex-6 FPGA User Manual

Transceiver and Tool Overview

Overview

The Virtex®-6 FPGA GTH transceiver is highly configurable and tightly integrated with
the programmable logic resources of the FPGA. It provides these features to support a
wide variety of applications:
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The Xilinx® CORE Generator™ tool includes a Wizard to automatically configure GTH
transceivers to support configurations for different protocols or perform custom
configuration (see
Figure 1-1
(XC6VHX255T).
Virtex-6 FPGA GTH Transceivers User Guide
UG371 (v2.0) February 16, 2010
Current Mode Logic (CML) serial drivers/buffers with configurable termination and
voltage swing
Support for multiple industry standards with the following line rates:
• 2.488 Gb/s to 2.795 Gb/s
• 9.953 Gb/s to 11.18 Gb/s
One PLL per GTH Quad
GTH lanes within a Quad can be configured with different line rates that are integer
multiples of each other (i.e., full line rate and line rate/4)
Linear equalizer with adaptive gain control and programmable boost
Selectable DFE with three TAPs that can either be controlled manually or by an
automatic adaptive engine
Three-tap FIR filter for the TX driver
Support for pre-cursor and post-cursor pre-emphasis
Optional built-in PCS features
• 8B/10B encoder/decoder with comma alignment
• 64B/66B block based on the IEEE 802.3-2008 Clause 49 implementation
• Raw mode (non-encoded datapath)
• PRBS generator and checker
Configurable fabric interface width
DRP and management interface to access the configuration registers
Virtex-6 FPGA GTH Transceiver Wizard, page
shows the GTH transceiver placement in an example Virtex-6 FPGA device
www.xilinx.com
Chapter 1
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