Top-Level Architecture; Transmit Architecture; Receive Architecture; Figure 2-1: Transmit Architecture - Xilinx RocketIO X User Manual
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Top-Level Architecture
Transmit Architecture
The transmit architecture for the PCS is shown in
bypassing particular blocks, consult the block function section for that particular block.
TXP
PMA
TXN
Convert
TXSCRAM64B66BUSE
TXGEARBOX64B66BUSE
Receive Architecture
The receive architecture for the PCS is shown in
bypassing particular blocks, consult the block function section for that particular block.
PMA/PCS Boundary
Sync State Machine
SLIP
RXCLK0
Comma Detect
Align
RXRECCLK
42
PMA
Attribute
Load
Gearbox
PMA
Scrambler
TX_BUFFER_USE
TXPOLARITY
Figure 2-1: Transmit Architecture
8B/10B
Decode
10G
10G
Block
Descr
Sync
HOLDOFF
RXBLOCKSYNCUSE,
RXVALUEDETUSE
Figure 2-2: Receive Architecture
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Chapter 2: Digital Design Considerations
Figure
6x40 bit
TXFIFO
10G Encode
TXENC8B10BUSE
TXENC6466USE
Reset
Control
Figure
Channel Bonding & Clock
Correction
RX Elastic
Buffer
16x52
RXDEC8B10BUSE,
RX_BUFFER_USE
RXDESCRAM64B66BUSE
2-1. For information about
TXUSRCLK
TXUSRCLK2
TXDATA
8B/10B
Encode
TXRESET
UG035_CH3_01_092903
2-2. For information about
Reset Control
10G
Decode
Fabric
RXDEC6466USE
UG035_CH3_02_092903
RocketIO™ X Transceiver User Guide
UG035 (v1.5) November 22, 2004
RXDATA
RXUSRCLK
RXUSRCLK2
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