Receive Data Path 32-Bit Alignment - Xilinx RocketIO User Manual

R
47
4-byte clock
High-Speed Serial Trace Design
119
HSPICE
I
119
Implementation Tools
J
Jitter
41
and BREFCLK
and use of DCM with REFCLK
deterministic and random, defined
105 106
parameters
,
PCB trace length mismatch
K
141
K-Characters, valid (table)
L
57
Latency, Data Path
M
121
MGT Package Pins
90
Miscellaneous Signals
33
Modifiable Primitives (table)
Multiplexed Clocking Scheme
56
with DCM
56
without DCM
P
119
Par
Passive Filtering 109
107
PCB Design Requirements
Ports & Attributes (by function)
8B/10B encoding/decoding
89
buffers, fabric interface
81
channel bonding
clock correction 74
85
CRC
68
SERDES alignment
77
synchronization logic
Ports (defined)
82
CHBONDDONE
83
CHBONDI
83
CHBONDO
150
ENCHANSYNC
112
ENMCOMMAALIGN
ENPCOMMAALIGN
LOOPBACK
POWERDOWN
RXBUFSTATUS
RXCHARISCOMMA
RXCHARISK
RXCHECKINGCRC
RXCLKCORCNT
RXCOMMADET
RXCRCERR
RXDISPERR
39
RXLOSSOFSYNC
105
RXNOTINTABLE
RXPOLARITY
112
RXREALIGN
RXRECCLK
RXRUNDISP
TXBUFERR
TXBYPASS8B10B
TXCHARDISPMODE
TXCHARDISPVAL
TXCHARISK
TXFORCECRCERR
TXINHIBIT
TXKERR
TXPOLARITY
TXRUNDISP
24
Ports (table)
Power Supply
passive filtering
power conditioning
voltage regulation
Pre-emphasis
available values
overview
scope screen captures
R
62
Random Jitter (RJ)

Receive Data Path 32-bit Alignment

Receiver Buffer
Reference Clock
generating
oscillator (Epson), for LVPECL
oscillator (Pletronics), for LVDS
Reset/Power Down
RocketIO transceiver
additional resources
analog design considerations
www.xilinx.com
1-800-255-7778
81
69
69
91
117
89
72
64
88
77 83
,
72
88
65
78 83
,
65
91
71
57
64
89
62
63
63
64
88
91
64
91
64
109
107
107
102
102
103 104
,
106
93
89
116
116
116
58
18
101
143
application notes
28
attributes (table)
basic architecture and capabilities
22 126
block diagram
,
channel bonding (channel alignment)
146
characterization reports
39
clocking
communications standards supported
CRC (Cyclic Redundancy Check)
default attribute values (tables)
design notes
117
analog
93
digital
digital design considerations
33
modifiable primitives
number of MGTs per device type
PCB design requirements
24
ports (table)
117
powering
143
related online documents
58
reset/power down
simulation and implementation
valid control characters (K-characters)
141
133
valid data characters
white papers 147
112
Routing Serial Traces
S
SERDES Alignment
68
overview
68
ports and attributes
101
Serial I/O Description
68
Serializer
Setup/Hold Times of Inputs Relative to Clock
127
119
Simulation Models
119
SmartModels
Synchronization Logic
76
overview
77
ports and attributes
T
127
Timing Parameters
105
Total Jitter (DJ + RJ)
Transmitter and Elastic (Receiver) Buffers
89
Transmitter Buffer (FIFO)
RocketIO™ Transceiver User Guide
UG024 (v2.3.2) June 24, 2004
21
79
21
83
33
39
21
107
119
89