Resetting The Transmit Datapath; Resetting The Receive Datapath - Xilinx Virtex-6 FPGA User Manual

Resetting the Transmit Datapath

The transmit datapath of the GTH transceiver must be reset under these conditions:
•
•
Figure 2-10
X-Ref Target - Figure 2-10
Note relevant to
1.
Follow these steps to reset the transmit datapath in the GTH transceiver:
1.
2.
3.

Resetting the Receive Datapath

The reset datapath of the GTH transceiver must be reset under these conditions:
•
•
•
Figure 2-11
X-Ref Target - Figure 2-11
Note relevant to
1.
Virtex-6 FPGA GTH Transceivers User Guide
UG371 (v2.0) February 16, 2010
After a line rate change
When the clock going into the TXUSERCLKIN port changes
shows the reset sequence for the transmit datapath.
T X P O W E R D O W N [ 1 : 0 ] < n >
T X C T R L A C K < n >
T X B F R E S E T < n >
Figure 2-10: GTH Reset for the Transmit Datapath
Figure 2-10:
The TXCTRLACK<n> signal can be High for more than 1 DCLK clock cycle.
Change TXPOWERDOWN<n>[1:0] to 2'b10 and wait for TXCTRLACK<n> to go
High.
Assert TXBUFRESET<n> for one TXUSERCLKIN clock cycle.
Change TXPOWERDOWN<n>[1:0] to 2'b00. The transmitter is ready for normal
operation.
After a line rate change
When the clock going into the RXUSERCLKIN port changes
When the receiver CDR loses lock as a result of:
• The remote link powering up
• Disconnecting and connecting RXN/RXP serial pins
shows the reset sequence for the receive datapath.
R X P O W E R D O W N < n > [ 1 : 0 ]
R X C T R L A C K < n >
R X B F R E S E T < n >
Figure 2-11: GTH Reset for the Receive Datapath
Figure 2-11:
The RXCTRLACK<n> signal can be High for more than 1 DCLK clock cycle.
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2 Õ b 0 0 2 Õ b 1 0
2 Õ b 0 0 2 Õ b 1 0
Reset and Initialization
2 Õ b 0 0
G 3 7 1 _ c 2 _ 0 7 _ 0 8 0 8 0 9
2 Õ b 0 0
G 3 7 1 _ c 2 _ 0 8 _ 0 8 0 8 0 9
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