ST STM32L4+ Series Reference Manual page 2247

RM0432
The Arm
•
SWJ-DP: serial wire / JTAG debug port
•
AHP-AP: AHB access port
•
ITM: instrumentation trace macrocell
•
FPB: Flash patch breakpoint
•
DWT: Data watchpoint trigger
•
TPIU: Trace port unit interface (available on larger packages, where the corresponding
pins are mapped)
•
ETM: Embedded Trace Macrocell (available only on STM32L4+ Series devices larger
packages, where the corresponding pins are mapped)
It also includes debug features dedicated to the STM32L4+ Series:
•
Flexible debug pinout assignment
•
MCU debug box (support for low-power modes, control over peripheral clocks, etc.)
Note: For further information on debug functionality supported by the Arm
to the Cortex
TRM (see
57.2 Reference Arm
•
Cortex
search for "Cortex
•
Arm
•
Arm
57.3 SWJ debug port (serial wire and JTAG)
The STM32L4+ Series core integrates the serial wire / JTAG debug port (SWJ-DP). It is an
®
Arm standard CoreSight debug port that combines a JTAG-DP (5-pin) interface and a SW-
DP (2-pin) interface.
•
The JTAG debug port (JTAG-DP) provides a 5-pin standard JTAG interface to the AHP-
AP port.
•
The serial wire debug port (SW-DP) provides a 2-pin (clock + data) interface to the
AHP-AP port.
In the SWJ-DP, the two JTAG pins of the SW-DP are multiplexed with some of the five JTAG
pins of the JTAG-DP.
® ®
Cortex -M4 core provides integrated on-chip debug support. It is comprised of:
®
-M4-r0p1 Technical Reference Manual and to the CoreSight Design Kit-r0p1
Section 57.2: Reference Arm
®
documentation
®
-M4 r0p1 Technical Reference Manual (TRM),
®
-M4 Technical Reference Manual" at http://infocenter.arm.com
®
Debug Interface V5
®
CoreSight Components Technical Reference Manual
®
documentation).
RM0432 Rev 6
Debug support (DBG)
® ®
Cortex -M4 core, refer
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