Jtag / Emulation; Device Configurations And Initialization; Device Reset - Texas Instruments AM62A7 Hardware Design Manual

JTAG

5.1 JTAG / Emulation

Relevant documentation for the JTAG/Emulation:
• Emulation and Trace Headers Technical Reference Manual
• XDS Target Connection Guide
• Boundary Scan Test Specification (IEEE-1149.1)
• AC Coupled Net Test Specification (IEEE-1149.6)
5.1.1 Configuration of JTAG / Emulation
The IEEE Standard 1149.1-1990, IEEE Standard Test Access Port and Boundary-Scan Architecture (JTAG)
interface can be used for boundary scan and emulation. The boundary scan implementation is compliant with
both IEEE-1149.1 and 1149.6. Boundary scan can be used regardless of the device configuration.
As an emulation interface, the JTAG port can be used in various modes:
• Standard emulation: requires only five standard JTAG signals
• HS-RTDX emulation: requires five standard JTAG signals plus EMU0 and/or EMU1. EMU0 and/or EMU1 are
bidirectional in this mode.
• Trace port: The trace port allows real-time dumping of certain internal data. The trace port uses the EMU pins
to output the trace data.
Emulation can be used regardless of the device configuration.
For supported JTAG clocking rates, see the device-specific TRM.
5.1.2 System Implementation of JTAG / Emulation
The JTAG and Emulation pins on this processor are in same power domains. The TDI, TDO, TCK, TMS, TRSTn,
EMU0 and EMU1 I/Os are powered by the VDDSHV_MCU domain. VDDSHV_MCU can be configured either 1.8
V or 3.3 V.
For most other system-level implementation details, see the
Manual.
5.1.3 JTAG Termination
For terminating the JTAG interface signal, see the Pin Connectivity Requirements section in the Terminal
Configuration and Functions chapter of the device-specific data sheet.
It is recommended to provision for connecting the JTAG during using test points when a JTAG connector is not
used.

6 Device Configurations and Initialization

When the voltage rails and the required clocks are present and stable, the processor reset may be deasserted
(released) to start the processor boot process.

6.1 Device Reset

The processor can be reset in several ways. The methods are described in detail in the device-specific data
sheet and TRM.
The processor includes three external reset input pins (MCU_PORz, MCU_RESETz, and RESETz_REQ) and
three reset status output pins (MCU_RESETSTATz, PORz_OUT and RESETSTATz). Be sure to provide the
terminations recommended in the Pin Connectivity Requirements section of device-specific data sheet.
For MCU_PORz, 3.3 V input can be applied, but the input thresholds are still a function of the 1.8 V I/O supply
voltage (VDDS_OSC0).
Additional reset modes are available through internal registers and emulation.
Note that TI recommends implementing RESET using ANDing logic for on-board Media and Data Storage
devices and other peripherals as applicable. One of the AND gate input is controlled by processor general-
purpose input/output (GPIO) pin with provision to isolate. The other AND gate input is the Main Domain
warm reset status output (RESETSTATz) Signal. Ensure the reset inputs are terminated as per the device
recommendations.
8 Hardware Design Guide for AM62A7/AM62A3 Devices
Emulation and Trace Headers Technical Reference
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SPRAD85 – MARCH 2023
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