Analog Devices SHARC ADSP-2136 Series Hardware Reference Manual page 358

Accuracy
Duty Cycle
The and
PWMAx
pairs of PWM output signals on the
switch reluctance mode.
• The two's-complement integer value in the
the duty cycle of the signals on the
• The two's-complement integer value in the
the duty cycle of the signals on
The duty cycle registers are programmed in two's-complement integer
counts of the fundamental time unit,
of the high side PWM signal produced by the two-phase timing unit over
half the PWM period. The duty cycle register range is from:
(–PWMPERIOD ÷ 2 – PWMDT) to (+PWMPERIOD ÷ 2 + PWMDT)
which, by definition, is scaled such that a value of 0 represents a 50%
PWM duty cycle. The switching signals produced by the two-phase tim-
ing unit are also adjusted to incorporate the programmed dead time value
in the register. The two-phase timing unit produces active low sig-
PWMDT
nals so that a low level corresponds to a command to turn on the
associated power device.
Output Enable
The register contains four bits (0 to 3) that can be used to individ-
PWMSEG
ually enable or disable each of the 4 PWM outputs. If the associated bit of
the register is set (=1), then the corresponding PWM output is dis-
PWMSEG
abled, regardless of the value of the co rresponding duty cycle register. This
PWM output signal remains disabled as long as the corresponding
enable/disable bit of the
changes to this register only become effective at the start of each PWM
10-22
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registers directly control the duty cycles of the two
PWMBx
register is set. In single update mode,
PWMSEGx
ADSP-2136x SHARC Processor Hardware Reference
for the ADSP-21362/3/4/5/6 Processors
to pins when not in
PWM_Ax PWM_Bx
PWMAx
and
PWM_AH PWM_AL
PWMBx
and
PWM_BH PWM_BL
, and define the desired on-time
PCLK
registers controls
pins.
registers control
pins.