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Peripherals Routed Through the DAI
in the
register is cleared (= 0), the se rial port does not compand the
MTCCSx
output during the channel's receive time slot.
SPORT Receive Select Registers (MRxCSx)
Each bit, 31–0, set (= 1) in one of the four
an active receive channel, 127–0, on a multichannel mode serial port.
When the
MRxCSx
word in that channel's position of the data stream and loads the word into
the
buffer. When a channel's bit in the
RXSPx
(= 0), the serial port ignores any input during the channel's receive time
slot.
SPORT Receive Compand Registers (MRxCCSx)
Each bit, 31–0, set (= 1) in the
panded receive channel, 127–0, on a multichannel mode serial port.
When one of the four
nel, the serial port applies the companding from the
received word in that channel's position of the data stream. When a chan-
nel's bit in the
MRxCCSy
compand the input during the channel's receive time slot.
SPORT Divisor Registers (DIVx)
This register, shown in
divisor and clock divisor.
31 30 29 28 27 26
15 14 13 12 11 10
CLKDIV (15–1)
Clock Divisor
Figure A-19. DIVx Register
A-46
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register activates a channel, the serial port receives the
MRxCCSy
registers activate companding for a chan-
MRxCCSy
registers are cleared (= 0), the serial port does not
Figure A-19
allows programs to set the frame sync
25
24 23 22 21 20 19 18 17 16
9
8
7
6
5
ADSP-2136x SHARC Processor Hardware Reference
for the ADSP-21362/3/4/5/6 Processors
registers corresponds to
MRCSx
register is cleared
MRxCSx
registers corresponds to a com-
DTYPE
FSDIV (31–16)
Frame Sync Divisor
4
3
2
1
0
selection to the
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