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data into the 64-bit shift register. The input to the shift register is con-
nected to
SRCx_TDM_OP_I
By connecting the
a large shift register is created, which is clocked by
TDM Input Daisy Chain
In TDM input port, several SRCs can be daisy-chained together and con-
nected to the serial input port of a SHARC processor or other processor
(Figure
12-4). The SRC IP contains a 64-bit parallel load shift register.
When the
SRCx_FS_IP_I
right data into the 64-bit shift register. The input to the shift register is
connected to
SRCx_DATA_IP_I
. By connecting the
SRCx_TDM_IP_O
of the next SRC, a large shift register is created, which is clocked by
.
SRCx_IP_CLK_I
The number of SRCs that can be daisy-chained together is limited
by the maximum frequency of
MHz. For example, if the output sample rate, f
eight SRCs could be connected since 512 f
ADSP-2136x SHARC Processor Hardware Reference
www.BDTIC.com/ADI
for the ADSP-21362/3/4/5/6 Processors
Asynchronous Sample Rate Converter
, and the output is connected to
to the
SRCx_DAT_OP_O
pulse arrives, each SRC parallel loads its left and
, while the output is connected to
SRCx_DATA_IP_I
of the next SRC,
SRCx_TDM_OP_I
SRCx_CLK_OP_I
to the
, which is about 25
SRCx_CLK_xx_I
, is 48 kHz, up to
S
is less than 25 MHz.
S
.
SRCx_DAT_OP_O
.
SRCx_TDM_IP_O
12-15
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