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/* TX Transfer Control Blocks */
.var tx_tcb1[4] = 0,BUFSIZE,1,tx_buf1a;
.var tx_tcb2[4] = 0,BUFSIZE,1,tx_buf1b;
/* RX Transfer Control Blocks */
.var rx_tcb1[4] = 0,BUFSIZE,1,rx_buf0a;
.var rx_tcb2[4] = 0,BUFSIZE,1,rx_buf0b;
/* Main code section */
.global _main;
.SECTION/PM seg_pmco;
_main:
r0 = 0; /* Clear CP registers before enabling chaining */
dm(CPSP0A) = r0;
dm(CPSP1A) = r0;
/* SPORT Loopback: Use SPORT0 as RX & SPORT1 as TX */
/* initially clear SPORT control register */
r0 = 0x00000000;
dm(SPCTL0) = r0;
dm(SPCTL1) = r0;
dm(SPMCTL01) = r0;
SPORT_DMA_setup:
/* set internal loopback bit for SPORT0 & SPORT1 */
bit set ustat3 SPL;
dm(SPMCTL01) = ustat3;
/* Configure SPORT1 as a transmitter */
/* internally generating clock and frame sync */
/* CLKDIV = [fPCLK(167 MHz)/4xFSCLK(8.325 MHz)]-1 = 0x0004 */
/* FSDIV = [FSCLK(8.325 MHz)/TFS(260 kHz)]-1 = 31 = 0x001F */
R0 = 0x001F0004; dm(DIV1) = R0;
ustat4 = SPEN_A| /* Enable Channel A */
SLEN32| /* 32-bit word length */
FSR| /* Frame Sync Required */
SPTRAN| /* Transmit on enabled channels */
ADSP-2136x SHARC Processor Hardware Reference
www.BDTIC.com/ADI
for the ADSP-21362/3/4/5/6 Processors
Serial Ports
6-59
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