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Programming Model
3. Keep the clock and the frame sync input of the serial inputs and/or
the PDAP connected to low, by setting proper values in the SRU
registers.
4. Refer to
5. Enable the channel's
6. Rout all of the required inputs to the IDP by writing to the SRU
registers
7. Start the DMA by setting
• The
PDAP is required).
• The global
standard DMA on the selected channel.
• The global
Starting a Ping-Pong DMA Transfer
To start a ping-pong DMA transfer from the FIFO to memory:
1. Clear the FIFO by setting (= 1) the
IDP_CTL1
2. While the global
the values for the following DMA parameter registers that corre-
spond to channels 7–0.
3. Keep the clock and the frame sync input of the serial inputs and/or
the PDAP connected to low, by setting proper values in the SRU
registers.
4. Refer to
8-28
www.BDTIC.com/ADI
"Setting Miscellaneous Bits"
IDP_ENx
bit (bit 31 in
IDP_PDAP_EN
IDP_DMA_EN
bit (bit 7 in the
IDP_EN
register).
IDP_DMA_EN
"Setting Miscellaneous Bits"
ADSP-2136x SHARC Processor Hardware Reference
for the ADSP-21362/3/4/5/6 Processors
above.
and
bit settings.
IDP_DMA_ENx
IDP_PP_CTL
bit of the
IDP_CTL1
IDP_CTL0
bit (bit 31 in the
IDP_FFCLR
and
bits are cleared (=0), set
IDP_EN
above.
register if the
register to enable
register).
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