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Peripheral Registers
Table A-10. PWMCTLx Register Bit Descriptions (Cont'd)
Bit
Name
4–3
Reserved
5
PWM_IRQEN
15–6
Reserved
PWM Status Registers (PWMSTATx)
These 16-bit, read-only registers, shown in
Table
A-11, report the status of the phase and mode for each PWM
group.
15 14 13 12
PWM_PAIRSTAT
Pair Mode Status
Figure A-12. PWMSTATx Register
Table A-11. PWMSTATx Register Bit Descriptions
Bit
Name
0
PWM_PHASE
1
Reserved
2
PWM_PAIRSTAT
15–3
Reserved
A-26
www.BDTIC.com/ADI
Description
Enable PWM Interrupts. Enables interrupts.
0 = Interrupts not enabled
1 = Interrupts enabled
11 10
9
8
7
6
5
4
Description
PWM Phase Status. Set during operation in the second half of
each PWM period. Allows programs to determine the particular
half-cycle (first or second) during implementation of the PWM-
SYNC interrupt service routine, if required.
0 = First half
1 = Second half
PWM Paired Mode Status.
0 = Inactive paired mode
1 = Active paired mode
ADSP-2136x SHARC Processor Hardware Reference
for the ADSP-21362/3/4/5/6 Processors
Figure A-12
and described in
3
2
1
0
PWM_PHASE
Phase Status
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