Tcb Chain Loading Access; Iop Register Access Arbitration - Analog Devices SHARC ADSP-2136 Series Hardware Reference Manual

I/O Processor Register Access
ISR_Routine:
R0 = 0x0;
dm(SPICTL) = R0;
lcntr=10, do (pc,1) until lce;
nop;
rti;

TCB Chain Loading Access

Table 2-17 lists the time required to load a specific TCB from the internal
memory into the DMA controller. During this time, the IOD bus is
locked and cannot be interrupted.

IOP Register Access Arbitration

Since the I/O processor's registers arepart of the processor's memory map,
buses access these registers as locations in memory. While these registers
act as memory-mapped locations, they are separate from the processor's
internal memory and have different bus access. One bus can access one
I/O processor register at a time. When there is contention among the
buses for access to the same I/O processor register, the processor arbitrates
register access as follows.
1. DMD bus accesses (highest priority)
2. PMD bus accesses
3. IOD bus accesses (lowest priority)
Note that internal memory block access arbitration is different—the high-
est priority is in favor of the IOD followed by the DMD and finally the
PMD buses.
2-34
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/* disable SPI */
ADSP-2136x SHARC Processor Hardware Reference
for the ADSP-21362/3/4/5/6 Processors