Analog Devices SHARC ADSP-2136 Series Hardware Reference Manual page 255

Without disabling the SPI:
1. Disable DMA and clear the FIFO by writing 0x80 to the
register. This ensures that any data from a previous DMA opera-
tion is cleared before configuring a new DMA operation.
2. Clear the
abling SPI. This can be done by ORing 0xc0000 with the present
value in the
clear the
3. Clear all errors by writing to the W1C-type bits in the
register. This ensures that error bits
SPIDMACx
4. Reconfigure the
the
RXSPI
5. Configure DMA by writing to the DMA parameter registers and
the
SPIDMACx
Slave Select Timing
When the processor is configured as an SPI slave, the SPI master must
drive an
SPICLK
parameters, please refer to the ADSP-2136x SHARC Processor Data Sheet.
As shown in Figure
(T2), and the sequential transfer delay time (T3) must always be greater
than or equal to one-half the
successive word transfers (T4) is two
measured from the last active edge of
edge of
SPICLK
configuration of the SPI (
ADSP-2136x SHARC Processor Hardware Reference
www.BDTIC.com/ADI
for the ADSP-21362/3/4/5/6 Processors
/ registers and the buffer status without dis-
RXSPIx TXSPIx
registers. Use the
SPICTLx
/ registers and the buffer status.
RXSPIx TXSPIx
registers are cleared when a new DMA is configured.
register to remove the clear condition on
SPICTL
/ register bits.
TXSPI
register.
signal that conforms with
7-6, the
SPIDS
SPICLK
of the next word. This calculation is independent from the
,
CPHASE SPIMS
Serial Peripheral Interface Ports
and
RXFLSH
and
SPIOVF
Figure 7-6. For exact timing
lead time (T1), the
period. The minimum time between
periods. This time period is
SPICLK
of one word to the first active
SPICLK
, and so on).
SPIDMAC
bits to
TXFLSH
SPISTAT
in the
SPIUNF
lag time
SPIDS
7-31