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Input Data Port Registers
The input data port (IDP) provides an additional input path to the pro-
cessor core. The IDP can be configured as 8 channels of serial data or 7
channels of serial data and a single channel of up to a 20-bit wide parallel
data.
Input Data Port DMA Control Registers
For information on these registers, see
ters" on page
2-6.
Input Data Port Control Register 0 (IDP_CTL0)
Use this register to configure and enable the IDP and each of its channels.
The register is shown in
31 30 29 28 27 26 25 24
IDP_SMODE7 (31–29)
Channel 7 Serial Mode Select
IDP_SMODE6 (28–26)
Channel 6 Serial Mode Select
15 14 13 12
IDP_SMODE2 (16–14)
Channel 2 Serial Mode Select
IDP_SMODE1 (13–11)
Channel 1 Serial Mode Select
IDP_SMODE0 (10–8)
Channel 0 Serial Mode Select
IDP_EN
Global IDP Enable
Figure A-20. IDP_CTL0 Register
ADSP-2136x SHARC Processor Hardware Reference
www.BDTIC.com/ADI
for the ADSP-21362/3/4/5/6 Processors
"Standard DMA Parameter Regis-
Figure A-20
and described in
23 22 21 20 19 18 17 16
11 10
9
8
7
6
5
4
Registers Reference
Table
A-19.
IDP_SMODE2 (16–14)
IDP_SMODE3 (19–17)
Channel 3 Serial Mode Select
IDP_SMODE4 (22–20)
Channel 4 Serial Mode Select
IDP_SMODE5 (25–23)
Channel 5 Serial Mode Select
3
2
1
0
IDP_NSET (3–0)
Number of FIFO entries
IDP_BHD
Buffer Hang Disable
IDP_DMA_EN
Global IDP DMA Enable
IDP_CLROVER
Clear FIFO Overflow
A-47
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