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B INTERRUPTS
This chapter provides a listing of the registers that are used to configure
and control programmable interrupts. For information on interrupt vector
tables and the core interrupt registers, see the SHARC Processor Program-
ming Reference.
Programmable Interrupt Control
Registers
The following sections provide descriptions of the programmable inter-
rupts that are used in the ADSP-2136x processors. These registers allow
programs to substitute the default interrupts for some other interrupt
source. For information on the interrupt registers and the interrupt vector
table, see
Appendix B,
Table B-1
lists the locations to be programmed in the programmable
interrupt control registers (
a corresponding processor interrupt location.
Table B-1
also defines the
select the source for each priority interrupt. Priority programming can be
accomplished by changing the sources for each priority interrupt. For
ADSP-2136x SHARC Processor Hardware Reference
www.BDTIC.com/ADI
for the ADSP-21362/3/4/5/6 Processors
Interrupts.
) to route a peripheral interrupt source to
PICR
bits which should be programmed to
PICR
B-1
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