Analog Devices SHARC ADSP-2136 Series Hardware Reference Manual page 304

Programming Model
3. The program clears (= 0) the channel's
IDP_CTL1
4. Reprogram the DMA registers for finished DMA channels.
More than one DMA channel may have completed during this
time period. For each channel, a bit is latched in the
or
DAI_IRPTL_H
grammed. If any of the channels are not used, then their clock and
frame syncs should be held low.
5. Read the
rupts have been generated.
• If the value(s) are not zero, repeat step 4.
• If the value(s) are zero, continue to step 6.
6. Re-enable the
7. Exit the ISR.
If a zero is read in step 5 (no more interrupts are latched), then all of the
interrupts needed for that ISR have been serviced. If another DMA com-
pletes after step 5 (that is, during steps 6 or 7), as soon as the ISR
completes, the ISR is called again because the OR of the latched bits will
not be nonzero again. DMAs in progress run to completion.

If step 5 is not performed, and a DMA channel expires during step
4, then, when IDP DMA is re-enabled, (step 6) the completed
DMA is not reprogrammed and its buffer overruns.
8-30
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register which has finished.
registers. Ensure that the DMA registers are repro-
or
DAI_IRPTL_L DAI_IRPTL_H
bit in the
IDP_DMA_EN
ADSP-2136x SHARC Processor Hardware Reference
for the ADSP-21362/3/4/5/6 Processors
bit in the
IDP_DMA_ENx
DAI_IRPTL_L
registers to see if more inter-
register (set to 1).
IDP_CTL