Analog Devices SHARC ADSP-2136 Series Hardware Reference Manual page 528

Peripherals Routed Through the DAI
Table A-18. SPMCTLxy Register Bit Descriptions
Bit Name
0 MCEA
4–1 MFD
11–5 NCH
12 SPL
15–13 Reserved
A-44
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Description
Multichannel Mode Enable. Standard and multichannel modes only.
One of two configuration bits that enable and disable multichannel
mode on serial port channels. See also, OPMODE on page A-26.
0 = Disable multichannel operation
1 = Enable multichannel operation if OPMODE = 0
Multichannel Frame Delay. Sets the interval, in number of serial clock
cycles, between the multichannel frame sync pulse and the first data
bit. These bits provide support for different types of T1 interface
devices. Valid values range from 0 to 15 with bits SPMCTL01[4:1],
SPMCTL23[4:1], or SPMCTL45[4:1].
Values of 1 to15 correspond to the number of intervening serial clock
cycles. A value of 0 corresponds to no delay. The multichannel frame
sync pulse is concurrent with first data bit.
Number of Multichannel Slots (minus one). Selects the number of
channel slots (maximum of 128) to use for multichannel operation.
Valid values for actual number of channel slots range from 1 to 128.
Use this formula to calculate the value for NCH:
NCH = Actual number of channel slots – 1.
SPORT Loopback Mode. Enables if set (= 1) or disables if cleared (=
0) the channel loopback mode. Loopback mode enables developers to
run internal tests and to debug applications. Loopback only works
under the following SPORT configurations:
• SPORT0 (configured to receive or transmit) together with
SPORT1 (configured to transmit or receive). SPORT0 can only be
paired with SPORT1, controlled via the SPL bit in the SPMCTL01
register.
• SPORT2 (as a receiver or transmitter) together with SPORT3 (as a
transmitter or receiver). SPORT2 can only be paired with SPORT3,
controlled via the SPL bit in the SPMCTL23 register.
• SPORT4 (configured to receive or transmit) together with
SPORT5 (configured to transmit or receive). SPORT4 can only be
paired with SPORT5, controlled via the SPL bit in the SPMCTL45
register. Either of the two paired SPORTs can be set up to transmit
or receive, depending on their SPTRAN bit configurations.
ADSP-2136x SHARC Processor Hardware Reference
for the ADSP-21362/3/4/5/6 Processors