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DAI Signal Routing Unit Registers
Table A-47. Group F Sources – Pin Output Enable
Selection Code Source Signal
000000 (0x0)
LOW
000001 (0x1)
HIGH
000010 (0x2)
MISCA0_O
000011 (0x3)
MISCA1_O
000100 (0x4)
MISCA2_O
000101 (0x5)
MISCA3_O
000110 (0x6)
MISCA4_O
000111 (0x7)
MISCA5_O
001000 (0x8)
SPORT0_CLK_PBEN_O
001001 (0x9)
SPORT0_FS_PBEN_O
001010 (0xA)
SPORT0_DA_PBEN_O
001011 (0xB)
SPORT0_DB_PBEN_O
001100 (0xC)
SPORT1_CLK_PBEN_O
001101 (0xD)
SPORT1_FS_PBEN_O
001110 (0xE)
SPORT1_DA_PBEN_O
001111 (0xF)
SPORT1_DB_PBEN_O
010000 (0x10) SPORT2_CLK_PBEN_O
010001 (0x11) SPORT2_FS_PBEN_O
010010 (0x12) SPORT2_DA_PBEN_O
010011 (0x13) SPORT2_DB_PBEN_O
010100 (0x14) SPORT3_CLK_PBEN_O
010101 (0x15) SPORT3_FS_PBEN_O
010110 (0x16) SPORT3_DA_PBEN_O
010111 (0x17) SPORT3_DB_PBEN_O
011000 (0x18) SPORT4_CLK_PBEN_O
011001 (0x19) SPORT4_FS_PBEN_O
A-104
www.BDTIC.com/ADI
Description (Source Selection)
Logic level low (0)
Logic level high (1)
Miscellaneous control A0 output
Miscellaneous control A1 output
Miscellaneous control A2 output
Miscellaneous control A3 output
Miscellaneous control A4 output
Miscellaneous control A5 output
SPORT 0 clock output enable
SPORT 0 frame sync output enable
SPORT 0 data channel A output enable
SPORT 0 data channel B output enable
SPORT 1 clock output enable
SPORT 1 frame sync output enable
SPORT 1 data channel A output enable
SPORT 1 data channel B output enable
SPORT 2 clock output enable
SPORT 2 frame sync output enable
SPORT 2 data channel A output enable
SPORT 2 data channel B output enable
SPORT 3 clock output enable
SPORT 3 frame sync output enable
SPORT 3 data channel A output enable
SPORT 3 data channel B output enable
SPORT 4 clock output enable
SPORT 4 frame sync output enable
ADSP-2136x SHARC Processor Hardware Reference
for the ADSP-21362/3/4/5/6 Processors
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