Analog Devices SHARC ADSP-2136 Series Hardware Reference Manual page 543

Table A-26. TMxSTAT Register Bit Descriptions (Cont'd)
Bit Name
9 TIM0EN Timer 0 Disable
10 TIM1EN Timer 1 Enable
11 TIM1EN Timer 1 Disable
12 TIM2EN Timer 2 Enable
13 TIM2EN Timer 2 Disable
31–11 Reserved
Sample Rate Converter Registers
The sample rate converter (SRC) is composed of five registers which are
described in the following sections.
SRC Control Registers (SRCCTLx)
The control registers (read/write) control the operating modes,
SRCCTLn
filters, and data formats used in the sample rate converter. For n = 0, the
register controls the SRC0 and SRC1 modules and for n = 1 it controls the
SRC2 and SRC3 modules (x = 0, 2 andy = 1, 3). The bit settings for these
registers are shown in
ADSP-2136x SHARC Processor Hardware Reference
www.BDTIC.com/ADI
for the ADSP-21362/3/4/5/6 Processors
Figure A-27 and described in
Registers Reference
Description
Write one to disable timer 0
Write one to enable timer 1
Write one to disable timer 1
Write one to enable timer 2
Write one to disable timer 2
Table A-27.
A-59